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Digital Design with VHDL

This presentation by Amir Masoud Gharehbaghi delves into the intricacies of digital design using VHDL. It covers essential concepts such as concurrent and sequential statements, signal assignments, component instantiation, and procedural calls. The guide includes detailed explanations of Mealy FSM implementation, subprogram declarations, package definitions, and various types like records and access types. With practical examples and code snippets, this resource serves as a valuable tool for engineers and students seeking to enhance their understanding of VHDL for digital design.

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Digital Design with VHDL

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  1. Digital Design with VHDL Presented by: Amir Masoud Gharehbaghi Email: amgh@mehr.sharif.edu

  2. Concurrent Statements • Concurrent Signal Assignment • Component Instantiation Statement • Generate Statement • Process Statement • Block Statement • Concurrent Procedure Call Statement • Concurrent Assert Statement

  3. Sequential Statements • Signal Assignment Statement • Variable Assignment Statement • IF Statement • Case Statement • Loop Statement • Wait Statement • Procedure Call Statement

  4. Sequential Statements (cont.) • Next Statement • Exit Statement • Return Statement • Assertion Statement • Report Statement • Null Statement

  5. Subprogram Declaration subprogram_specification IS subprogram_declarative_part BEGIN sequential statements END [subprogram_type] [designator]; subprogram_specification ::= PROCEDURE designator [ ( parameter_list ) ] | FUNCTION designator [ ( parameter_list ) ] RETURN type_name designator ::= identifier | operator_symbol

  6. Mealy FSM using Function PROCESS (present , x) FUNCTION nxt_gen(present : state; x: BIT) RETURN state IS VARIABLE nxt: state; BEGIN CASE present IS WHEN a => IF x = '0' THEN nxt := a; ELSE nxt := b; END IF; … END CASE; RETURN nxt; END nxt_gen; BEGIN nxt <= nxt_gen(present, x); IF present = c AND x = '1' THEN z <= '1'; ELSE z <= '0'; END IF; END PROCESS;

  7. Mealy FSM using Procedure PROCESS (present , x) PROCEDURE nxt_gen(present: state; x: BIT; SIGNAL nxt: OUT state) IS BEGIN CASE present IS WHEN a => IF x = '0' THEN nxt <= a; ELSE nxt <= b; END IF; … END CASE; END nxt_gen; BEGIN nxt_gen(present, x, nxt); IF present = c AND x = '1' THEN z <= '1'; ELSE z <= '0'; END IF; END PROCESS;

  8. Concurrent Procedure Call ARCHITECTURE test1 of test IS PROCEDURE apply(…) IS BEGIN … END; BEGIN apply(…); END;

  9. Package Declaration PACKAGE identifier IS package_declarative_part END [PACKAGE] [package_name] PACKAGE BODY package_name IS package_body_declarative_item END [PACKAGE BODY] [package_name]

  10. std_logic package PACKAGE std_logic_1164 IS TYPE std_ulogic IS ( 'U', -- Uninitialized 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance 'W', -- Weak Unknown 'L', -- Weak 0 'H', -- Weak 1 '-' -- Don't care ); TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) OF std_ulogic; FUNCTION "and" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; END std_logic_1164;

  11. std_logic Package Body PACKAGE BODY std_logic_1164 IS TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic; CONSTANT and_table : stdlogic_table := ( -- ---------------------------------------------------- -- | U X 0 1 Z W L H - | | -- ---------------------------------------------------- ( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X | ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W | ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | - | );

  12. std_logic Package Body FUNCTION "and" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l; ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r; VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH ); BEGIN FOR i IN result'RANGE LOOP result(i) := and_table (lv(i), rv(i)); END LOOP; RETURN result; END "and"; END std_logic_1164;

  13. Alias Declaration ALIAS identifier [ : type] IS name ; -> alias : an alternative name given to - an object - an indexed part of it - a slice of it

  14. Record Type TYPE identifier IS RECORD element_declaration { element_declaration } END RECORD; element_declaration ::= identifier : type ;

  15. Record Example TYPE instruction_format IS RECORD opc : opcode ; mode : mode_type ; adr : address_type ; END RECORD; … SIGNAL instr: instruction_format; … Instr.adr <= “10110000”;

  16. ACCESS Type (pointers) TYPE node; TYPE pointer IS ACCESS node; TYPE node IS RECORD data: data_type; link: pointer; END RECORD;

  17. ACCESS Type (cont.) VARIABLE head: pointer := NULL; … head := NEW node; … Head.link := NEW node;

  18. Assert & Report Statement ASSERT condition REPORT “message” SEVERITY severity_level ; REPORT “message” SEVERITY severity_level ; severity_level ::= NOTE | WARNING | ERROR | FAILURE

  19. Setup & Hold Time ASSERT NOT((clk = ‘1’ AND NOT clk’STABLE) AND data’STABLE(setup_time)) REPORT “Setup Time Violation” SEVERITY WARNING; ASSERT NOT(data’EVENT AND clk = ‘1’ AND NOT clk’STABLE(hold_time)) REPORT “Hold Time Violation” SEVERITY WARNING;

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