Lecture #25a

1. Lecture #25a OUTLINE • Interconnect modeling • Propagation delay with interconnect • Inter-wire capacitance • Coupling capacitance effects – loading, crosstalk • Transistor scaling • Silicon-on-insulator (SOI) technology • Interconnect scaling Reading (Rabaey et al.): Sections 3.5, 3.6. Note that he has an entire chapter (4 – The Wire) devoted to interconnects in which he elaborates on some of the slides in this lecture. Note also pp. 229-232 – Perspective and Summary

2. Interconnects • An interconnect is a thin-film wire that electrically connects 2 or more components in an integrated circuit. • Interconnects can introduce parasitic (unwanted) components of capacitance, resistance, and inductance. These “parasitics” detrimentally affect • performance (e.g. propagation delay) • power consumption • reliability • As transistors are scaled down in size and the number of metal wiring layers increases, the impact of interconnect parasitics increases. • Need to model interconnects, to evaluate their impact

3. V DD Interconnect Resistance & Capacitance • Metal lines run over thick oxide covering the substrate • contribute RESISTANCE & CAPACITANCE to the output node of the driving logic gate PMOS NMOS GND

4. Wire Resistance L H W

5. Interconnect Resistance Example • Typical values of Rn and Rp are ~10 kW, for W/L = 1 • … but Rn, Rp are much lower for large transistors (used to drive long interconnects with reasonable tp) • Compare with the resistance of a 0.5mm-thick Al wire: • R =  / H = (2.7 -cm) / (0.5 m) = 5.4 x 10-2 /  • Example: L = 1000 m, W = 1 mm • Rwire = R(L/ W) • = (5.4 x 10-2 /)(1000/1) = 54 W

6. Wire Capacitance: The Parallel Plate Model single wire over a substrate: electric field lines tdi Relative Permittivities

7. Parallel-Plate Capacitance Example • Oxide layer is typically ~500 nm thick • Interconnect wire width is typically ~0.5 m wide (1st level) • capacitance per unit length = 345 fF/cm = 34.5 aF/m • Example: L = 30 m • Cpp1 fF (compare with Cn~ 2 fF)

8. Fringing-Field Capacitance For W / tdi < 1.5, Cfringe is dominant Wire capacitance per unit length:

9. Modeling an Interconnect Problem: Wire resistance and capacitance to underlying substrate is spread along the length of the wire “Distributed RC line” We will start with a simple model…

10. Lumped RC Model • Model the wire as single capacitor and single resistor: • Cwire is placed at the end of the interconnect • adds to the gate capacitance of the load • Rwire is placed at the logic-gate output node • adds to the MOSFET equivalent resistance Rwire Cwire substrate

11. Cascaded CMOS Inverters w/ Interconnect Equivalent resistanceRdr (rwire, cwire, L) Vin Cintrinsic Cfanout Using “lumped RC” model for interconnect: Rdr Rwire Cintrinsic Cwire Cfanout

12. Effect of Interconnect Scaling • Interconnect delay scales as square of L • minimize interconnect length! • If W is large, then it does not appear in RwireCwire • Capacitance due to fringing fields becomes more significant • as W is reduced; Cwire doesn’t actually scale with W for small W

13. The 0.38 factor accounts for the fact that the wire resistance and capacitance are distributed. Propagation Delay with Interconnect Using the lumped-RC interconnect model: In reality, the interconnect resistance & capacitance are distributed along the length of the interconnect.  The interconnect delay is actually less than RwireCwire:

14. B C A oxide Si substrate Wire B has additional sidewall capacitance to neighboring wires Wire C has additional capacitance to the wire above it Interconnect Wire-to-Wire Capacitance Wire A simply has capacitance (Cpp + Cfringe) to substrate

15. k=3.6 Tungsten Plugs Intel 0.25µm Process (Al) 5 Layers - Tungsten Vias Source: Intel Technical Journal 3Q98 Tungsten Plugs Intel 0.13µm Process (Cu) Source: Intel Technical Journal 2Q02 Wiring Examples - Intel Processes Advanced processes: narrow linewidths, taller wires, close spacing  relatively large inter-wire capacitances

16. Effects of Inter-Wire Capacitance • Capacitance between closely spaced lines leads to two major effects: • Increased capacitive loading on driven nodes (speed loss) • Unwanted transfer of signals from one place to another through capacitive coupling “crosstalk” • We will use a very simple model to estimate the magnitude of these effects. In real circuit designs, very careful analysis is necessary.

17. ground Approaches to Reducing Crosstalk • Increase inter-wire spacing (decrease CC) • Decrease field-oxide thickness (decrease CC/C2) • …but this loads the driven nodes and thus decreases circuit speed. • Place ground lines (or VDD lines) between signal lines SiO 2 Silicon substrate

18. Transistor Scaling • Steady advances in manufacturing technology (particularly lithography) have allowed for a steady reduction in transistor size. ~13% reduction/year (0.5 every 4-6 years) • How should transistor dimensions and supply voltage (VDD) scale together? Average minimum L of MOSFETs vs. time

19. Scenario #1: Constant-Field Scaling • Voltages and MOSFET dimensions are scaled by the same factor S >1, so that the electric field remains unchanged tox / S xj xj / S VDD VDD / S L / S Doping NA NA S

20. Impact of Constant-Field Scaling (a) MOSFET gate capacitance: (b) MOSFET drive current: æ ö W 2 ¢ - æ ö W V V I ç ÷ ( ) ( ) S ¢ ¢ ¢ ¢ 2 µ - @ µ ç ÷ DD T DSAT I C V V SC ç ÷ ¢ DSAT ox DD T ox L L è S ø S è ø S (c) Intrinsic gate delay : • Circuit speed improves by S

21. area required per transistor # of transistors per unit area Impact of Constant-Field Scaling (cont’d) (d) Device density: (e) Power dissipated per device: (f) Power density: • Power consumed per function is reduced by S2

22. log IDS Low VT High VT VT cannot be aggressively scaled down! IOFF,low VT IOFF,high VT VGS 0 VDD VT Scaling? • Low VT is desirable for high ON current: IDSAT (VDD - VT) 1 <  < 2 • Low VT is desirable for high ON current: IDSAT (VDD - VT) 1 <  < 2 • But high VT is needed for low OFF current:

23. Since VT cannot be scaled down aggressively, the power-supply voltage (VDD) has not been scaled down in proportion to the MOSFET channel length:

24. Scenario #2: Generalized Scaling • MOSFET dimensions are scaled by a factor S >1; Voltages (VDD & VT) are scaled by a factor U >1 L = L / S ; W = W / S ; tox = tox / S VDD = VDD / U Note:U is slightly smaller than S (a) MOSFET drive current: (b) Intrinsic gate delay:

25. Impact of Generalized Scaling (c) Power dissipated per device: (d) Power dissipated per unit area: • Reliability (due to high E-fields) and power density are issues!

26. 0.85V VDD=0.75V Intrinsic Gate Delay (CgateVDD/ IDSAT)

27. Transistors are fabricated in a thin single-crystal Si layer on top of an electrically insulating layer of SiO2 Simpler device isolation  savings in circuit layout area Low pn-junction & wire capacitances  faster circuit operation No “body effect” Higher cost TSOI Silicon-on-Insulator (SOI) Technology

28. Global Interconnects • For global interconnects (long wires used to route VDD, GND, and voltage signals across a chip), the wire resistance dominates the resistance of the driving logic gate (i.e.Rwire >> Rdr) RwireCwireL2 • The length of the longest wires on a chip increases slightly (~20%) with each new technology generation. In order to minimize increases in global interconnect delay, the cross-sectional area of global interconnects has not been scaled, i.e. W and H are not scaled down for global interconnects => Place global interconnects in separate planes of wiring

29. wire delay increases gate delay Intel 0.13µm Process (Cu) Source: Intel Technical Journal 2Q02 Interconnect Technology Trends • Reduce the inter-layer dielectric permittivity • “low-k” dielectrics (er 2) • Use more layers of wiring • average wire length is reduced • chip area is reduced