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55:035 Computer Architecture and Organization

55:035 Computer Architecture and Organization. Lecture 2. Outline. Information representation Arithmetic operations (addition and subtraction) Instruction Formats Addressing Modes Assembly Language Programming Basic input/output operations Subroutine linkage.

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55:035 Computer Architecture and Organization

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  1. 55:035Computer Architecture and Organization Lecture 2

  2. Outline • Information representation • Arithmetic operations (addition and subtraction) • Instruction Formats • Addressing Modes • Assembly Language Programming • Basic input/output operations • Subroutine linkage 55:035 Computer Architecture and Organization

  3. Integer non-Negative Number Representation The most significant bit The least significant bit 55:035 Computer Architecture and Organization

  4. Decimal-to-Binary Conversion V is divided by 2  the reminder is the least significant bit of B bnbn-1…b1b0 The quotient is again divided by 2  the reminder is the next bit of B bnbn-1…b1b0 … The process is repeated up to and including the step in which the quotient becomes 0: bnbn-1…b1b0 55:035 Computer Architecture and Organization

  5. Real non-Negative Number Representation 55:035 Computer Architecture and Organization

  6. Decimal-to-Binary Conversion To convert a fixed-point decimal number into binary, the integer and fraction parts are handled separately. • The integer part is converted as the integer number • The fractional part is converted by multiplying it and then fractional parts of its products by 2: • The part of the product to the left of the decimal point, which is either 0 or 1, is a bit in the binary representation. • The first bit generated is the bit immediately to the right of the binary point. • The next bit generated is the second bit to the right, and so on • The process is repeated until the required accuracy is attained 55:035 Computer Architecture and Organization

  7. Convert ( 927.45 ) 10 927 1 - - - - - - - - - = 463 + - - - 1 LSB 2 2 463 1 - - - - - - - - - = 231 + - - - 1 2 2 231 1 - - - - - - - - - = 115 + - - - 1 2 2 115 1 - - - - - - - - - = 57 + - - - 1 2 2 1 57 - - - - - - 28 + - - - = 1 2 2 0 28 0 - - - - - - = 14 + - - - 2 2 0 14 - - - - - - = 7 + - - - 0 2 2 7 1 - - - = 3 + - - - 1 2 2 1 3 - - - 1 + - - - = 1 2 2 1 1 - - - 0 + - - - = 1 MSB 2 2 0.45 ´ 2 = 0.90 0 MSB 0.90 ´ 2 = 1.80 1 1 0.80 ´ 2 = 1.60 1 0.60 ´ 2 = 1.20 0 0.20 ´ 2 = 0.40 0.40 ´ 2 = 0.80 0 0.80 ´ 2 = 1.60 1 LSB ( 927.45 ) = ( 1110011111.0111001 ¼ ) 10 2 55:035 Computer Architecture and Organization

  8. Signed Numbers Representation • The leftmost bit bn-1 is the sign bit: • 0 for positive numbers and 1 for negative numbers • Positive values have identical representation • Negative values have different representation 55:035 Computer Architecture and Organization

  9. 1’s-complement representation (negative values are obtained by complementing each bit of the corresponding positive number): +5 = 0101 -5 = 1010 2’s-complement representation (negative values are obtained by subtracting the corresponding positive number from 2n): Signed Numbers Representation Sign-and-magnitude representation (negative values are represented by changing the most significant bit): +5 = 0101 -5 = 1101 55:035 Computer Architecture and Organization

  10. Signed Numbers Representation Sign and b b b b magnitude 1' s complement 2' s complement 3 2 1 0 + 7 + 7 + 7 0 1 1 1 + 6 + 6 + 6 0 1 1 0 + 5 + 5 + 5 0 1 0 1 + 4 + 4 + 4 0 1 0 0 + 3 + 3 + 3 0 0 1 1 + 2 + 2 + 2 0 0 1 0 + 1 + 1 + 1 0 0 0 1 + 0 + 0 + 0 0 0 0 0 - 0 - 7 - 8 1 0 0 0 - 1 - 6 - 7 1 0 0 1 - 2 - 5 - 6 1 0 1 0 - 3 - 4 - 5 1 0 1 1 - 4 - 3 - 4 1 1 0 0 - 5 - 2 - 3 1 1 0 1 - 6 - 1 - 2 1 1 1 0 - 7 - 0 - 1 1 1 1 1 55:035 Computer Architecture and Organization

  11. Addition of Positive Numbers 0 1 0 1 + 0 + 0 + 1 + 1 0 1 1 1 0 Carry-out Figure 2.2. Addition of 1-bit numbers. 55:035 Computer Architecture and Organization

  12. S/M and 1’s-Complement Representation • Since we can’t perform addition and subtraction in the same manner, development of special circuitry for subtraction is needed • 1’s-Complement Representation does not allow a universal representation of 0: there are +0 and -0 that become formally different values 55:035 Computer Architecture and Organization

  13. 2’s Complement Conversion to Decimal • Positive Numbers: Just ignore the 0, repeat the process • studied earlier. • For negative numbers: Example 1101 • Discard the 1 which represents the sign: 101 • Subtract 1 • 101 • -001 • 100 • Complement 100=>011 • Obtain decimal value (011)B=3D • Remember is a negative value 1101 = -3 55:035 Computer Architecture and Organization

  14. Decimal Conversion to 2’s Complement • Positive Numbers • Find signed representation • Negative numbers • Subtract number from 2n • Find signed representation 55:035 Computer Architecture and Organization

  15. Addition of 2’s-Complement Numbers • To add two numbers, add their n-bit representations, ignoring the carry-out signal from the most significant bit (MSB) position. Note: The sum will be correct in the 2’s complement representation as long as the answer is in the range -2n-1 through 2n-1-1 55:035 Computer Architecture and Organization

  16. Subtraction of 2’s-Complement Numbers • To subtract two numbers X and Y, that is, to perform X-Y, form the 2’s-complement of Y and then add it to X according to the addition rule. Note: The result will be correct in the 2’s complement representation as long as the answer is in the range -2n-1 through 2n-1-1 55:035 Computer Architecture and Organization

  17. 2’s Complement System 0 1 N - 1 N - 2 2 (a) Circle representation of integers modN 0000 1111 0001 1110 0010 0 - 1 + 1 - 2 + 2 1101 0011 - 3 + 3 - 4 + 4 1100 0100 - 5 + 5 1011 0101 - 6 + 6 - 7 + 7 - 8 1010 0110 1001 0111 Figure 2.3. Modular number systems and the 2's-complement system. 1000 (b) Mod 16 system for 2's-complement numbers 55:035 Computer Architecture and Organization

  18. Addition of 2’s-Complement Numbers 0000 1111 0001 1110 0010 0 -1 +1 -2 +2 1101 0011 -3 +3 -4 +4 1100 0100 -5 +5 1011 0101 -6 +6 -7 +7 -8 1010 0110 1001 0111 1000 3+2=5; 3’2=0011; 2’2=0010 Good method as long as the results is less than 2(N-1)-1 3| 0011 + 2| +0010 5| 0 0101 Carry-out bit is ignored to obtain the correct result 55:035 Computer Architecture and Organization

  19. Addition of 2’s-Complement Numbers 0000 1111 0001 1110 0010 0 -1 +1 -2 +2 1101 0011 -3 +3 -4 +4 1100 0100 -5 +5 1011 0101 -6 +6 -7 +7 -8 1010 0110 1001 0111 1000 7-3=4; 7’2=0111; -3’2=1101 (if this were an unsigned number 1101=13) 7 | 0111 +(-3)| +1101 (8 -3= 5=> 1 101) 4| 10100 Carry-out bit is ignored to obtain the correct result 55:035 Computer Architecture and Organization

  20. 2’s-Complement Addition • The 2’s-Complement System is the most efficient for addition and subtraction of signed numbers because both can be performed in the same manner for both positive and negative numbers • Same manner=Same circuitry=Less $$$$ 55:035 Computer Architecture and Organization

  21. 6| 0110 5| +0101 11|= 1011 overflow -7| 1001 1001 +( -1)| -0001  1111 -8|=11000 no overflow Overflow in Integer Arithmetic • In the 2’s-complement system n bits can represent the values in the range • For example: • When the result of an arithmetic operation is outside this range, an arithmetic overflow has occurred 55:035 Computer Architecture and Organization

  22. Overflow in Integer Arithmetic • Overflow can occur only when adding two numbers that have the same sign • A simple way to detect overflow is to examine the signs of the two summands (X and Y ) and the sign of the result S (S=X+Y). • When both operands X and Y have the same sign, an overflow occursif the sign of sum S is not the same as the signs of X and Y. • The carry-out signal from the sign-bit position is not a sufficient indicator of overflow when adding signed numbers 55:035 Computer Architecture and Organization

  23. ( + 4 ) 0 0 1 0 ( + 2 ) 0 1 0 0 ( ) 0 0 1 1 + 3 1 0 1 0 ( - 6 ) ( - 2 ) 0 1 0 1 ( + 5 ) 1 1 1 0 ( ) + 7 1 0 1 1 ( - 5 ) 0 1 1 1 1 1 1 0 ( - 2 ) 1 1 0 1 ( - 3 ) 1 0 0 1 ( - 7 ) 0 1 0 0 ( + 4 ) 1 1 0 1 1 1 0 1 ( - 3 ) 1 0 0 1 0 1 1 1 ( - 7 ) 0 1 0 0 ( + 4 ) 0 0 1 0 ( + 2 ) 0 0 1 0 ( ) 0 1 0 0 + 4 1 1 0 0 1 1 1 0 ( - 2 ) 0 1 1 0 0 1 1 0 ( + 6 ) ( + 3 ) 0 0 1 1 1 1 0 1 0 0 1 1 ( + 3 ) 1 0 0 1 1 0 0 1 ( - 7 ) 0 1 0 1 1 0 1 1 ( - 5 ) 1 1 1 0 ( - 2 ) 1 0 0 1 ( - 7 ) 1 0 0 1 0 0 0 1 ( + 1 ) 1 1 1 1 1 0 0 0 ( - 8 ) 0 0 1 0 0 0 1 0 ( + 2 ) 1 1 0 1 0 0 1 1 ( - 3 ) ( ) 0 1 0 1 + 5 2’s-Complement Addition and Subtraction (a) (b) + + (c) (d) + + (e) + - (f) - + (g) - + (h) - + (i) - + (j) - + 55:035 Computer Architecture and Organization

  24. Comparison of Signed Representations 55:035 Computer Architecture and Organization

  25. Character Representation • Each character is encoded by 8 bits • American Standards Committee on Information Interchange (ASCII) encoding system – 7 bits encoding • The 8th (most significant) bit is used to encode characters from different alphabets and some extra special symbols 55:035 Computer Architecture and Organization

  26. Binary Coded Decimal (BCD) Decimal BCD code • Encoding of decimal digits digit 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 55:035 Computer Architecture and Organization

  27. Hexadecimal Numbers • Base 16 ={0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F} • (Z3Z2Z1Z0)H= (Z3x163)+(Z3x162)+(Z3x161)+(Z3x160)= (Z3x4096)+(Z3x256)+(Z3x16)+(Z3x1) • Example: (A34E)H= (A x163)+(3 x162)+(4 x161)+(E x160)= (Ax4096)+(3x256)+(4x16)+(E x1)= (10x4096)+(3x256)+(4x16)+(14 x1)= 40960+768+64+14=41806. 55:035 Computer Architecture and Organization

  28. Hexadecimal Numbers Advantages • Easier to represent large numbers in compact manner • Close relationship to binary numbers Ex.: Find the binary representation of 110101101011101 110 1011 0101 1101 6D=6H 11D=BH 5D=5H 13D=CH (110101101011101)B=(6B5C)H 55:035 Computer Architecture and Organization

  29. Conversion Hexadecimal-Decimal • Hexadecimal to Decimal: As shown on previous slide • Decimal to HEX: Same process as with binary. Example: (1574)D=(?)H 1974 / 16 = 123 rem 6 123 / 16 = 7 rem 11 Hence (1574)D=(7B6)H 55:035 Computer Architecture and Organization

  30. Table of ASCII Characters 55:035 Computer Architecture and Organization

  31. Minimum Number of Bits 55:035 Computer Architecture and Organization

  32. ………………. Cells Memory Each cell can store 1 bit of information having the value 0 or 1 55:035 Computer Architecture and Organization

  33. Memory … … 0 n-1 Word is a group of n bits n is called the word length Modern computers have word length that typically range from 16 to 64 bits As a rule, the word length is a power of 2: 16, 32 or 64 bits 55:035 Computer Architecture and Organization

  34. Memory … … 0 7 Byte is a unit of 8 bits Word typically consists of 2 or 4 bytes (2 bytes for the IBM PC) Bits are seldom addressable individually Bytes have addresses that are used for accessing the memory to store or retrieve a single item of information 55:035 Computer Architecture and Organization

  35. Byte Addressability Successive byte locations in the memory have successive addresses Memory is byte-addressable Thus, successive byte locations have addresses 0, 1, 2, 3, 4,… If the word length of the machine is 32 bits, successive words are located at the aligned addresses 0, 4, 8, 12, … 55:035 Computer Architecture and Organization

  36. Memory n bits first word (0) second word (4) • • • i th word • • • last word 55:035 Computer Architecture and Organization

  37. Encoded Information 32 bits • • • b b b b 31 30 1 0 for positive numbers Sign bit: b = 0 31 for negative numbers b = 1 31 (a) A signed integer 8 bits 8 bits 8 bits 8 bits ASCII ASCII ASCII ASCII character character character character (b) Four characters 55:035 Computer Architecture and Organization

  38. Memory Usually numbers from 0 through 2k-1 for some suitable value of k are used as the addresses of successive locations (bytes) in the memory The 2kaddresses constitutes the address space of the computer, and the memory has up to 2kaddressable locations 55:035 Computer Architecture and Organization

  39. Example • k=3 then we can access 23=8 different addresses: Binary Decimal 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 55:035 Computer Architecture and Organization

  40. Memory Units 1K (Kbyte) = 210 (1,024) bytes 1M (Mbyte) = 220 (1,048,576) bytes = 1,024 K 1G (Gbyte) = 230 bytes = 1,024 M 1T (Tera) = 240 bytes = 1,024 G Example: 32-bit address generates an address space of 232 bytes =22 x 230= 4 x 1 G = 4 (Gigabytes) Example: 24-bit address generates an address space of 224 =24 x 220bytes = 16 x 1M= 16 M (Megabytes) 55:035 Computer Architecture and Organization

  41. Memory Units What if we want to address 3,000,000 bytes? 222 bytes =22 x 220= 4 x 1 M = 4 M > 3,000,000 bytes 221 bytes =21 x 220= 2 x 1 M = 2 M < 3,000,000 bytes Not enough addresses! 55:035 Computer Architecture and Organization

  42. Addresses Assignment • Big-endian assignment: lower byte addresses are used for the more significant (the leftmost) bytes of the words • Little-endian assignment: lower byte addresses are used for the less significant (the rightmost) bytes of the words 55:035 Computer Architecture and Organization

  43. Addresses Assignment W ord address Byte address Byte address 0 0 1 2 3 0 3 2 1 0 4 4 5 6 7 4 7 6 5 4 • • • • • • k k k k k k k k k k 2 - 4 2 - 4 2 - 3 2 - 2 2 - 1 2 - 4 2 - 1 2 - 2 2 - 3 2 - 4 (a) Big-endian assignment (b) Little-endian assignment 55:035 Computer Architecture and Organization

  44. Debug • Characteristics: • Is program provided by DOS • Used for testing and debug executable programs • Displays all program code and data in hexadecimal • Allows to execute programs step by step • Does not distinguish between lowercase and upper case • Commands: • D Display the contents of an area in memory • E Enter data into memory • Q Quit session • R Display the contents of one or more registers • T Trace the execution of one instruction • W Write program onto disk 55:035 Computer Architecture and Organization

  45. Debug Display Hex Address Hex Representation ASCII Representation 55:035 Computer Architecture and Organization

  46. Debug Display System Equipment same 55:035 Computer Architecture and Organization (54)16=“T”

  47. Debug Display Memory Size 55:035 Computer Architecture and Organization

  48. Debug Display Model ID FC = PC-AT 55:035 Computer Architecture and Organization

  49. Machine Instructions • A computer must have instructions capable of performing four types of operations: • Data transfers between the memory and the processor registers • Arithmetic and logic operations on data • Program sequencing and control • Input/Output (I/O) transfers 55:035 Computer Architecture and Organization

  50. Data Transfers: Possible Locations • Memory locations • Processor registers • Registers in the I/O subsystem • In the instruction itself (immediate data) Most of the time we identify a location by a symbolic name standing for its hardware binary address: • Memory Locations: LOCA, LOC, PLACE, A, VAR2, JOHN_SMITH • Processor register names: R0, R5, R10, … • I/O register names: DATAIN, OUTSTATUS 55:035 Computer Architecture and Organization

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