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ECNG1014/EE19D Digital Electronics

ECNG1014/EE19D Digital Electronics. Sequential Logic: Fundamentals. Specification of Sequential Systems.

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ECNG1014/EE19D Digital Electronics

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  1. ECNG1014/EE19DDigital Electronics Sequential Logic: Fundamentals EE19D Digital Electronics: Sequential Logic

  2. Specification of Sequential Systems • A logic network is combinational if its static behavior can be described by a set of Boolean equations, with each output variable expressed as a function of only the input variables. In this part of the note we will present logic networks that do not satisfy this definition. Such networks are called sequential networks. • Equations and tables that are used to describe them are time-based descriptions, in which a memory effect is taken into consideration, finite state automata theory has been used efficiently to describe sequential circuits. EE19D Digital Electronics: Sequential Logic

  3. A sequential circuit is a circuit in which decisions are made based on combinations of the current inputs as well as the past history of outputs. • A Finite state machine circuit is a sequential circuit which has an internal state, and whose outputs are functions of both the current inputs and its internal state. e.g a vending machine controller. • STATE: a grouping of individual binary bits embodying all the information about the past needed to predict current output based on current input. The state is the machine memory. • For the design of sequential circuits, there is a need to use circuit with a memory behavior, in which their outputs depends upon their previous states and inputs. A basic memory element is called a latch or bistable. EE19D Digital Electronics: Sequential Logic

  4. Just as gates are fundamental units of combinational logic, elementary memory units called SR latches (S: set, R: reset) are also for sequential networks. More complex memory elements are called flip-flops. • A sequential network consists of a combinational network and a digital memory made up of flip-flops for storing the previous states. • A flip-flop is a logic device capable of storing one binary digit of information. It may has one or more inputs. It has two outputs, know as Q and Q'. Its next state, Q(t+d), is a function of the present state Q(t) and the present input W(t), where d represents the inherent delay of the device caused by its finite signal propagation time from input to output. In that case of a synchronous flip-flop, the input-output relationship is defined in terms of clock pulses that provide synchronization at the expense of operational speed , since the clock period must be greater than the interval d of the flip-flop. Therefore, we have the next state Qn+1(tn+1), at clock pulse tn+1, as a function of the present state Qn(tn) and the present input Wn(tn) at the clock pulse tn. EE19D Digital Electronics: Sequential Logic

  5. Synchronous sequential networks are cyclic, with a period that is determined by a special signal called the clock. Quantizing times permit to establish a simple model of synchronous sequential networks: The state Model. An asynchronous sequential networks are self-timed networks that are not driven by a clock signal. RS Latches are small asynchronous networks. Figure 1 shows the difference between the two concepts. Figure 1. (a) Synchronous Behavior. (b) Asynchronous Behaviour. EE19D Digital Electronics: Sequential Logic

  6. The majority of today’s digital systems are synchronous, but more and more in the semiconductor industry there is a huge demand of fast chips with less power consumption: Asynchronous logic is adequate for such requirements. In order to study sequential networks it’s important to consider a logic gate with the effect of the delay (propagation time). An inverter will be considered as follows (figure 2): Figure 2: Inverter Model EE19D Digital Electronics: Sequential Logic

  7. The delay notation is useful in defining the basic sequential element. The clock is a sequential circuit for the generation of a stable reference signal called a square wave. The time interval of a repeating pattern is called the period T, and its reciprocal is known as the fundamental clock frequency. The signal’s active time, td, divided by its period is called the duty cycle. The active time interval is called a pulse and is bounded by a leading (rising) edge and a trailing (falling) edge. These concepts are illustrated in figure 3. V DD V x 50% 50% Gnd Propagation delay Propagation delay V DD 90% 90% V 50% 50% A Gnd 10% 10% t t r f Figure 3. Basic digital timing definitions EE19D Digital Electronics: Sequential Logic

  8. A sequential network can be represented by the following block diagram (figure 4) EE19D Digital Electronics: Sequential Logic

  9. The delay elements are detailed, with output signals named y1, y2, …………yk and referred to as state variables, and input signals denotes Y1, Y2……Yk. The present sate of the network is then given by k-tuple of state variables (y1, y2, y3…….yk); the next state (Y1, Y2, Y3……….Yk). Some of the output signals, Zis, may be equivalent to Yis. When we force all delays in a sequential network to be equal ( i.e di = d2 = d3 …….= dk = d) and force the input n-tuple and state k-tuple to change at the same time, we operate that network in the synchronous mode. EE19D Digital Electronics: Sequential Logic

  10. The combinational logic network accepts n inputs switching variables (W-vector) and p present state variables (y-vector) and generates m next state variables (Y-vector) and m output variables (Z-vector). The next state variables are function of the input variables and the present state variables, or Y=f(W,y). Similarly, the output variables are function of the input variables and the present state variables, or Z = h(W,y). the relationship between Yi and yi is defined as Yi(t) = yi(t+d) for asynchronous networks and Yi(n+1) = yi(n+1) for synchronous networks, where d represents the memory device inherent delay and n the clock interval. EE19D Digital Electronics: Sequential Logic

  11. The sequential systems can have up to 2k states, S = (S1, S2, S3, …..S2k), it is formally defined as a quintuple M = (W, Z, S, f, h), where W, Z, and S are finite, nonempty sets of inputs, outputs, and states, respectively. - fis the state transition function, such that Next state = f(W(t), Present State). - h is the output function. Because the number of states of the sequential systems studied in this course is always finite, we called such systems finite state machines. EE19D Digital Electronics: Sequential Logic

  12. Example 1. Consider a system whose input has two values, called a and b, and whose output also has two values, 0 and 1. The output at time t is 1 if the number of b’s in the input time function x(t) is even, 0 otherwise. A time-behaviour specification of this system is: PS: Present State and NS: Next State EE19D Digital Electronics: Sequential Logic

  13. t 0 1 2 3 4 5 6 X(t) 3 5 7 8 3 6 1 Y(t) 5 2 4 2 5 6 3 Z(t) 8 7 1 1 9 2 5 Example 2. A serial adder is a sequential system in which the input at time i corresponds to digit i of both operands, and the output to digit i of the result, starting from the least-significant digit. For example, the input-output pair for a decimal serial adder with inputs 1638753 + 3652425 is EE19D Digital Electronics: Sequential Logic

  14. A complete description of the decimal serial adder is Input: x(t), y(t)  {0,1,2………..,9} Output: z(t)  {0,1,2………..,9} State: c(t)  {0,1} {the carry} Initial state: c(0) = 0 Functions: The transition and output functions are Question 1. Give a complete description of modulo-64 counter (Hint: Think first about the modulo operator) EE19D Digital Electronics: Sequential Logic

  15. Bistable Element • The simplest sequential circuit • One state variable, say, Q • Two states (Q=1, Q=0) Q is “locked” at a fixed value by the using the feedback arrangement 0,1 1,0 0,1 0,1 EE19D Digital Electronics: Sequential Logic

  16. 1 0 How do we control this .. There is no input! Can use an ingenious rotary switch Recall…. X = 0 => Z=Y’ (the inverter) X = 1 => Z=0 Use NOR as an inverter with X as a control, Y as inverter input!! X Z=(X+Y)’ Y EE19D Digital Electronics: Sequential Logic

  17. To get the SR Latch “Control” inputs force the relevant gate output to logic 0 Current Next S R Q QN Q* QN* 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 ------------ 0 0 Hold Mode (inverters on) Outputs forced to known values Reset Mode (clears Q) Set Mode (Sets Q) NOT USED EE19D Digital Electronics: Sequential Logic

  18. S-R latch symbols Of Latches and Flip-flops (Wak 7.2) NB: A LATCH is an asynchronous device.. Its operation is not dependent on a synchronizing clock NB: A FLIP-FLOP is a synchronous device. It has a well defined input that is used for a synchronizing (clock) signal EE19D Digital Electronics: Sequential Logic

  19. Why is S=R=1 not used?? • Because this forces both outputs to be zero simultaneously. This clearly is not in line to the two inverter feedback arrangement • MOST IMPORTANTLY: If we input sequence SR=11, 00 we have a completely symmetrical circuit. • One of two possibilities: • One of the outputs will --> 0 and the other (the fastest) -->1 • The outputs will oscillate in an attempt to decide which one will be zero and the other 1. • In both cases, the device is unusable since we cannot predict the output • NOTE: SR=11, 10 or 11,01 OK since outputs are forced EE19D Digital Electronics: Sequential Logic

  20. 1 0 0 0 0 0 0 1 At t=0 At t=0+ • Will try to --> 1 • Only the faster device will “win”. • If both are at same speed, will oscillate 0 0 0 0 EE19D Digital Electronics: Sequential Logic

  21. SR 00 01 10 11 0 0 d 1 1 0 d 1 0 Q 1 Q* Current Next S R Q QN Q* QN* 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 ------------ 0 0 Q* = S + R’Q State Table of SR latch Characteristic Eqn of SR latch Looks like a differential equation?? EE19D Digital Electronics: Sequential Logic

  22. Notation, characteristic equations • Q means “the next value of Q.” • “Excitation” is the input applied to a device that determines the next state. • “Characteristic equation” specifies the next state of a device as a function of its excitation. • S-R latch: Q = S + R´ · Q • State Table (transition table): Truth Table of next states as function of current states and excitation EE19D Digital Electronics: Sequential Logic

  23. D Q QN D Q Q D-Type Latch A modification that avoids unused input assignments D S Q R QN = or D-Type Latch Current Next S R Q QN Q* QN* 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 ------------ 0 0 Q* = S+R’Q =S + SQ =S =D Most sequential circuits utilise D-type latches and flip flops EE19D Digital Electronics: Sequential Logic

  24. D Q Q D Q Q E.G.: A 2-bit Counter Count bits: COUNT=Q1 Q0 Q0 SUM0 ao SUM0 a1 SUM1 bo b1 Q0 2-bit Adder PLS Q1 SUM1 Q1 0 RCO Excitation Logic Output Logic State Memory Word description The latch stores the current count This corresponds always to the Adder input a1a0. A pulse on b0 adds one to the present count. The resulting sum is stored in the latches, thus updating the count. RCO: Ripple Carry Out Asserted when max count reached 1.e. COUNT = 11 EE19D Digital Electronics: Sequential Logic

  25. I/P Current Next Current State State Output PLS Q1 Q0 SUM1 SUM0 Q1* Q0* RCO 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 Analysis via modified state table Intermediate values • NOTE: • PLS = 0: => Q1*=Q1, Q0* = Q0 i.e. no change in state • PLS = 1: => val(Q1*Q0*)= val(Q1Q0)+1 i.e. count EE19D Digital Electronics: Sequential Logic

  26. PLS 0 Q0 0 1 0 1 1 0 0 Q1 1 0 1 0 time Initial conditions req’d Timing Diagram (Functional) Assumption: Positive pulse on PLS is changed before output changes more than once. Must be shorter than propagation delay! These arrows show cause and effect EE19D Digital Electronics: Sequential Logic

  27. Q1 Q0 Q1 Q0 00 00 O1 O1 10 10 11 11 0 0 PLS PLS 1 1 Q1* Q0* I/P Current Next Current State State Output PLS Q1 Q0 Q1* Q0* RCO 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 0 1 1 1 1 1 1 0 0 0 1 0 1 0 1 1 0 0 1 1 0 1 1 1 1 1 1 0 0 0 Descriptions of Circuit State/Output Table Next State Equation: Work this out 0 1 0 1 1 1 0 0 Q0* = Q1*=Q1’Q0PLS+Q1PLS’+Q1Q0’ Output Equation RCO = Q1Q0 EE19D Digital Electronics: Sequential Logic

  28. PROBLEM…... • Cannot practically and reliably limit pulse width as required. • Need a tighter control on the latch to stop “runaway” changes of state when PLS=1. Output counts continually with change rate depending on propagation delays (unpredictable) • Solution (7.2.2.Wakerly): • Add an enable control input (controlled by a CLOCK signal in most sequential logic • Use alternatively enabled Master/Slave sections to eliminate runaway transitions • The above combine to break the continuous feedback which cause multiple transitions in sequential circuits EE19D Digital Electronics: Sequential Logic

  29. S Q S Q R QN C S Q C R QN S Q C R Q QN R Introduction to Flip flop = Latch with enable (clock) control C=0: Q*= Q, QN*=QN I.e. HOLD C=1: Q*=S+R’Q (SR FF enabled) or SR Latch with Enable The Enable input [1] allows us to block changes in FF input from affecting the FF output. [2] Allows us to synchronise changes in circuits with large no. of FFs (synchronous sequential logic) EE19D Digital Electronics: Sequential Logic

  30. D Q S Q R QN C QN D Q C QN D Q C Q D type Latch with Enable C=0: Q*= Q, QN*=QN I.e. HOLD C=1: Q*=Q (D FF enabled) or EE19D Digital Electronics: Sequential Logic

  31. Flip-flops • A flip-flop is a synchronous binary element that exhibits on sequential activity. Algebraic and tabular notation for flip-flops is also identical to that for latches, but where “present” and “next” are separated by gate delays for latches, the clock period is used: clocked flip-flops. • The clock signal used for flip-lops can be active high or low. But most of the flip-flops use a method of edge-triggering (transition from 0 to 1: or 1 to 0: ). Figure 5 gives an example of a positive edge pulse. EE19D Digital Electronics: Sequential Logic

  32. Figure 5. Generation of a positive edge pulse. EE19D Digital Electronics: Sequential Logic

  33. QM Q D master slave CLK D Q Q D Q C Q D Q C Q Master/Slave Structure (D-Type FF) QN • CLK de-asserted <=> master enabled, slave disabled • CLK asserted <=> master de-asserted, slave asserted • CLK --> 0 => Master accepts new data (QM*=D) no change in Q since slave disabled • CLK --> 1 => master disabled (QM*=QM I.e. HOLD) and QM transferred to slave (Q*=QM). QM fixed at last value of D before CLK --> 1 • MAX of 1 transition on Q per clock cycle. No runaway transitions • To outside world Q takes on new value on every positive CLK transition : positive edge triggered flip flop. EE19D Digital Electronics: Sequential Logic

  34. D CLK QM Q QN Typical Functional Timing Diagram • NB: • Use same Next State Equation, Q* = D but… • D is taken as last D before CLK -->1, Q* is effected immediately after CLK and remains fixed for entire next cycle EE19D Digital Electronics: Sequential Logic

  35. JK flip-flop • This flip-flop has tree inputs, the J, the K, and the clock and two complementary outputs, Q and Q’. The following example provides a detailed analysis for a positive edge, clock transition triggered JK flip-flop. EE19D Digital Electronics: Sequential Logic

  36. Most clocked FFs have one or more asynchronous inputs which operate independently of the synchronous inputs and clock input. These inputs can be used to set the flip-flop to 1 or to clear the flip-flop to zero at any time (figure 10). EE19D Digital Electronics: Sequential Logic

  37. Timing Parameters of a D Flip-Flop (binary cell): Set up time (tsu) is the minimum time interval from the stabilization of the DFF input to the triggering edge of the clock. Holt time (th) is the minimum time interval from the triggering edge of the clock to a subsequent change in the input to the cell. Pulse width (tw) is the minimum width of the synchronizing clock pulse Propagation delay (tp) is the time interval from the triggering edge of the clock to the stabilization of the new state (DFF out) EE19D Digital Electronics: Sequential Logic

  38. D Q Q D Q Q Synchronous 2-bit counter Q0 SUM0 ao SUM0 a1 SUM1 bo b1 Q0 2-bit Adder PLS Q1 SUM1 Q1 0 CLK RCO Excitation Logic Output Logic State Memory • CLK is pulse stream (in all synchronous circuits, assumed CLK never stops ) • PLS =1 => count proceeds. PLS=0 => count is frozen • Inputs (PLS) must change prior to CLK  NOT AT CLK  !! EE19D Digital Electronics: Sequential Logic

  39. CLK 0 0 1 PLS 1 1 1 0 Q0 0 0 0 1 1 1 0 0 Q1 1 0 0 1 1 Initial conditions req’d time EE19D Digital Electronics: Sequential Logic

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