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CS151 Introduction to Digital Design

CS151 Introduction to Digital Design. Chapter 3: Combinational Logic Design 3-1 Design Procedure. Overview. Part 1 – Design Procedure Steps Specification Formulation Optimization Technology Mapping Verification Manual Simulation Beginning Hierarchical Design

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CS151 Introduction to Digital Design

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  1. CS151Introduction to Digital Design Chapter 3: Combinational Logic Design 3-1 Design Procedure Created by: Ms.Amany AlSaleh

  2. Overview • Part 1 – Design Procedure • Steps • Specification • Formulation • Optimization • Technology Mapping • Verification • Manual • Simulation • Beginning Hierarchical Design • Technology Mapping - AND, OR, and NOT to NAND or NOR Created by: Ms.Amany AlSaleh

  3. Overview (continued) • Part 2 – Combinational Logic • Functions and functional blocks • Rudimentary logic functions • Decoding using Decoders • Implementing Combinational Functions with Decoders • Encoding using Encoders • Selecting using Multiplexers • Implementing Combinational Functions with Multiplexers Created by: Ms.Amany AlSaleh

  4. Combinatorial Logic Circuit m Boolean Inputs n Boolean Outputs Combinational Circuits • A combinational logic circuit has: • A set of m Boolean inputs, • A set of n Boolean outputs, and • n switching functions, each mapping the 2m input combinations to an output such that the current output depends only on the current input values. • A block diagram: Created by: Ms.Amany AlSaleh

  5. Design Procedure • Specification • Write a specification for the circuit if one is not already available. • Determine and name inputs. • Determine and name outputs. • Formulation (Truth table) • Derive a truth table or initial Boolean equations that define the required relationships between the inputs and outputs, if not in the specification. • Optimization • Simplify the resulting Boolean functions for each output. • Draw a logic diagram or provide a netlist for the resulting circuit using ANDs, ORs, and inverters. Created by: Ms.Amany AlSaleh

  6. Design Procedure • Technology Mapping (Section 3-4) • Map the logic diagram or netlist to the implementation technology selected. • Transform the logic diagram to a new diagram using the available implementation technology. • Verification (Section 3-6) • Verify the correctness of the final design manually or using simulation. Created by: Ms.Amany AlSaleh

  7. Example-1 Design a combinational circuit with 3 inputs and 1 output. The output must be logic 1 when the binary value of the inputs is less than 011(3) and logic 0 otherwise. Use only NAND Gates. Created by: Ms.Amany AlSaleh

  8. Optimization: Boolean Function for each output F = X’Y’ + X’Z’ Specification: 3 inputs :X, Y and Z 1 output: F (Formulation) Truth Table 3 inputs  23 rows Example-1 (Cont) Logic Diagram and Technology Mapping Created by: Ms.Amany AlSaleh

  9. Example-2 Design a BCD to Excess-3 code converter • Transforms BCD code for the decimal digits to Excess-3 code for the decimal digits • BCD code words for digits 0 through 9: 4-bit patterns 0000 to 1001, respectively • Excess-3 code words for digits 0 through 9: 4-bit patterns consisting of 3 (binary 0011) added to each BCD code word Created by: Ms.Amany AlSaleh

  10. Example-2 (Cont.) • In multiple output circuits, each output must be expressed separately as a function of all the input variables BCD-to-Excess-3 Code Converter 0 0 0 0 1 1 1 0 1 1 0 0 0 1 0 1 BCD code Excess-3 code Created by: Ms.Amany AlSaleh

  11. Example-2 (Cont.) • Specification: • 4 Inputs: A, B, C and D • 4 Outputs: W,X, Y and Z • Don’t cares: BCD 1010 to 1111 • Formulation (Truth Table) • 4 inputs  24 rows BCD only needs 10 rows Design of a BCD-to-Excess-3 Code Converter W= (5,6,7,8,9) X= (1,2,3,4,9) Y= (0,3,4,7,8) Z= (0,2,4,6,8) Created by: Ms.Amany AlSaleh

  12. Example-2 (Cont.) • OptimizationBoolean function for each output using K-maps. x C C w 1 1 1 0 1 3 2 0 1 3 2 1 1 1 1 W= (5,6,7,8,9) X= (1,2,3,4,9) Y= (0,3,4,7,8) Z= (0,2,4,6,8) 4 5 7 6 B 4 5 7 6 B X X X X X X X X 12 13 15 14 12 13 15 14 A A 1 X X 1 1 X X 8 9 11 10 8 9 11 10 D D C y C z 1 1 • W= A + BC + BD = A + B(C+D) • X = B’C + B’D + BC’D’ = B`(C+D) + BC`D` • Y = CD + C’D’ • Z = D’ 1 1 0 1 3 2 0 1 3 2 1 1 1 1 4 5 7 6 B 4 5 7 6 B X X X X X X X X 12 13 15 14 12 13 15 14 A A 1 X X 1 X X 8 9 11 10 8 9 11 10 D D Created by: Ms.Amany AlSaleh

  13. Example-2 (Cont.) • Draw the logic diagram • W= A + B(C+D) • X = B`(C+D) + BC`D` • Y = CD + C’D’ • Z = D’ Created by: Ms.Amany AlSaleh

  14. Example 3 Design a BCD-to-Seven-Segment Decoder. • A BCD-to-seven-segment-decoder is a combinational circuit that accepts a decimal digit in BCD and generates the appropriate output for the selection of segments that display the decimal digit. • Each digit is formed from 7 segments, each consisting of 1 LED that can be illuminated by digital signals. Created by: Ms.Amany AlSaleh

  15. Example 3 (Cont.) • Specification: • 4 Inputs (BCD bits): A, B, C and D • 7 Outputs (display segments): a, b, c, d, e, f and g • Don’t cares: BCD 1010 to 1111, can we really have them as don’t cares? g 1 1 1 1 1 1 1 BCD-to-7-Segment Decoder f 0 0 0 1 D e C d BCD code B c A b a Created by: Ms.Amany AlSaleh

  16. a f b g e c d Example 3 (Cont.) • List the segments that should be illuminated for each digit. 0 a,b,c,d,e,f 1 b,c 2 a,b,d,e,g 3 a,b,c,d,g 4 b,c,f,g 5 a,c,d,f,g 6 a,c,d,e,f,g 7 a,b,c 8 a,b,c,d,e,f,g 9 a,b,c,d,f,g Created by: Ms.Amany AlSaleh

  17. Example 3 (Cont.) • 2. Formulation (Truth table)To display the input BCD digit: • Which segment(s) should illuminate (be turned on)? • Which segment(s) should not illuminate (be turned off)? a f b g e c d Created by: Ms.Amany AlSaleh

  18. Example 3 (Cont.) • Optimization:Boolean Function for each output • a=? b=? c=? d=? • e=? f=? g=? • Draw the logic diagram Created by: Ms.Amany AlSaleh

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