Introduction to Digital IC Design

1. NATIONAL INSTITUTE OF TECHNOLOGY, TIRUCHIRAPPALLI – 620 015 (STB99061) 3-DAY TUTORIAL ON VERILOG HDL Organized by IEEE STUDENT BRANCH NIT TRICHY Introduction to Digital IC Design Er. S. Bibin Sam Paul Research Scholar NIT-T Department of Electronics and Communication Engineering

2. Outline of the Presentation • Abstract Levels of Electronic Design • Introduction to IC and VLSI Technology • Introduction to FPGA • Design of ASICs • HDL Design S.Bibin Sam Paul, IEEE Student Branch NIT-T

3. Abstract levels of Electronic Design S.Bibin Sam Paul, IEEE Student Branch NIT-T

4. Electronics-Abstract Levels • The study of electronics can be broken down into four abstract levels: Level 1 – Fundamental of Electricity Level 2 – Electronic Devices/Components Level 3 – Electronic Circuits Level 4 – Electronic System Design S.Bibin Sam Paul, IEEE Student Branch NIT-T

5. Level 1: Fundamentals of Electricity Level 1: Basics of Electricity Current – Andre’ Ampere’ Voltage – Alessandro Volta Resistance – George Ohm Power – James Watt Andre’ Ampere’ Georg Ohm Alessandro Volta Power Current James Watt Voltage Resistance S.Bibin Sam Paul, IEEE Student Branch NIT-T

6. Level 2: Electronic Devices/Components • Level 2 Electronic Components • Switches and Keyboard • Semiconductors • Transducers • Resistors • Capacitors • Electron Tubes • Magnetic Nikola Tesla Thomas Edison S.Bibin Sam Paul, IEEE Student Branch NIT-T

7. Electronic Circuit Components Connectors Printed Circuit Boards Integrated Circuits S.Bibin Sam Paul, IEEE Student Branch NIT-T

8. Level 3: Electronic Circuits • Level 3: Electronic Circuits • Signal Generators and Timers • Amplifiers • Digital Circuits • Power Supplies • Detectors and Mixers • Filters • Phase-locked Looks • Converters • Data Acquisition • Synthesizers James Clerk Maxwell Charles Wheatstone Gustav Kirchoff Robert Noyce S.Bibin Sam Paul, IEEE Student Branch NIT-T

9. Level 4: Electronic Systems • Level 4: Electronic Systems • Communications • Computers • Consumer • Industrial • Test and Measurement • Biomedical S.Bibin Sam Paul, IEEE Student Branch NIT-T

10. Electronic Systems • Consumer • Video Equipment • Audio Equipment • Personal • Automobile Electronics • Industrial • Manufacturing Equipment • Computer-Aided-Design • and Engineering CAD/CAE • Management • Communications Systems Radio Telecommunications Television Data Communications • Computers • Data Terminals • Computer Systems • Data Storage • Input/Output Devices • Biomedical • Patient Care • Diagnostics • Test and Measurement • General Test and • Measurement Equipment • Automated Test Systems S.Bibin Sam Paul, IEEE Student Branch NIT-T

11. Introduction to IC and VLSI Technology S.Bibin Sam Paul, IEEE Student Branch NIT-T

12. IC Products • Processors • CPU, DSP, Controllers • Memory chips • RAM, ROM, EEPROM • Analog • Mobile communication,audio/video processing • Programmable • PLA, FPGA • Embedded systems • Used in cars, factories • Network cards • System-on-chip (SoC) Images: amazon.com S.Bibin Sam Paul, IEEE Student Branch NIT-T

13. History: Semiconductor Devices & Technology • Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable • In 1945, Bell Labs established a group to develop a semiconductorreplacement for the vacuum tube. The group led by William Shockley, included, John Bardeen, Walter Brattainand others point-contact transistor S.Bibin Sam Paul, IEEE Student Branch NIT-T

14. History: Semiconductor Devices & Technology • In 1947 Bardeen, Brattain and Shockley succeeded in creating an amplifying circuit utilizing a Ge point-contact "transfer resistance“ device that later became known as a transistor • The transistor invented at Bell lab. in 1947 • In 1951 Shockley developed the junction transistor, a more practical form of the transistor. • By 1954 the transistor was an essential component of the telephone system and the transistor first appeared in hearing aids followed by radios. • In1956 the importance of the invention of the transistor by Bardeen, Brattain and Shockley was recognized by the Nobel Prize in physics S.Bibin Sam Paul, IEEE Student Branch NIT-T

15. History: Semiconductor Devices & Technology • 1958 - Integrated circuit invented • September 12th 1958 Jack Kilbyat Texas instrumenthad built a simple oscillator IC with five integrated components (resistors, capacitors, distributed capacitors and transistors) • Robert Noyce (Fairchild) is also considered as a co-inventor • In2000the importance of the IC was recognized when Kilby shared the Nobel prize in physics with two others. a simple oscillator IC S.Bibin Sam Paul, IEEE Student Branch NIT-T

16. History: Semiconductor Devices & Technology Jean Hoerni, a cofounder of Fairchild Semiconductor, invented the first planar, or flat, transistor in 1959. He developed a structure with N and P junctions formed in silicon.Over the junctions a thin layer of silicon dioxide was used as an insulator and holes were etched open in the silicon dioxide to connect to the junctions. In 1959, Robert Noyce also of Fairchild had the idea to evaporate a thin metal layer over the circuits created by Hoerni's process. The metal layer connected down to the junctions through the holes in the silicon dioxide and was then etched into a pattern to interconnect the circuit. Planar technology set the stage for complex integrated circuitsand is the process used today. The result was the best-performing transistor of its time. Image source: Fairchild Semiconductor S.Bibin Sam Paul, IEEE Student Branch NIT-T

17. History: Semiconductor Devices & Technology • 1960 - First MOSFET fabricated • Kahng and Atalla at Bell Labs fabricates the first MOSFET. • Integrating Multiple Components • Robert Noyce—cofounder of Fairchild Semiconductor and latercofounder of Intel— saw a way to use Hoerni’s process to combine multiple electronic components, including transistors, on a single piece of silicon. • Announced in 1961, this resistor-transistor logic (RTL) chip was one of the first commercial integrated circuits. • The one shown has four transistors (quadrants in the middle). The white lines are metal traces, which connect the transistors to the two resistors below (horizontal blue bar). The Apollo Guidance Computer used the chip. S.Bibin Sam Paul, IEEE Student Branch NIT-T

18. History: Semiconductor Devices & Technology 1962 - Transistor-Transistor Logic invented 1962 - Semiconductor industry surpasses $1-billion in sales At that time only a few simple gates offering primitive logic functions such as not, nand, nor etc. could be accommodated (SSI) 1963 - First Metal Oxide Semiconductor (MOS) IC S.Bibin Sam Paul, IEEE Student Branch NIT-T

19. History: Semiconductor Devices & Technology 1963 - CMOS invented • Frank Wanlassat Fairchild Semiconductor originated and published the idea of complementary-MOS (CMOS). • It occurred toWanlassthat a complementary circuit of NMOS and PMOS would draw very little current. Initially Wanlass tried to make a monolithic solution, but eventually he was forced to provethe concept with discrete devices. S.Bibin Sam Paul, IEEE Student Branch NIT-T

20. History: Semiconductor Devices & Technology In 1965 Gordon Moore, director of research and development at Fairchild Semiconductor wrote a paper for Electronics entitled"Cramming more componentsonto integrated circuits". 1965 - Moore's law S.Bibin Sam Paul, IEEE Student Branch NIT-T

21. History: Semiconductor Devices & Technology 1965 - Moore's law • In the paper Moore observed that "The complexity for minimum component cost has increased at a rate of roughly a factor of two per year". This observation became known as Moore's law, the number of components per IC double every year. • Moore's law was later amended to, the number of components per IC doubles every 18 months. • Moore's law hold to this day ?. S.Bibin Sam Paul, IEEE Student Branch NIT-T

22. History: Semiconductor Devices & Technology By 1970 MSI circuits with about a thousand transistors appeared By 1980 LSI circuits of approximately one hundred thousand devices were possible Integration Levels SSI: 10 gates MSI: 1000 gates LSI: 10,000 gates VLSI: > 10k gates This ultimately led the arena of VLSI S.Bibin Sam Paul, IEEE Student Branch NIT-T

23. VLSI Arena • A VLSI contains more than a million or so switching devices or logic gates • Early in the first decade of the 21st century, the actual number of transistors has exceeded 100 million • A piece of silicon (a chip) is typically about 1 centimeter on a side S.Bibin Sam Paul, IEEE Student Branch NIT-T

24. Benefits of VLSI Technology • Integration reduces manufacturing cost - (almost) no manual assembly • Integration improves the design • Lower parasitics = higherspeed • Lower power consumption • Physicallysmaller S.Bibin Sam Paul, IEEE Student Branch NIT-T

25. Introduction to FPGA S.Bibin Sam Paul, IEEE Student Branch NIT-T

26. Basic FPGA Architecture • Field Programmable Gate Array • Configurable Logic blocks (CLB), interconnection resources, and I/O pads. CLB Consist of • Look-up Tables (LUT) • Carry and Control Logic • Memory Elements FPGA S.Bibin Sam Paul, IEEE Student Branch NIT-T

27. FPGA Architecture Trends • Memories • Single & Dual-port RAMS • FIFO (first-in first-out) • ECC (error correcting codes) • Digital Signal Processors • Multipliers • Accumulators • Arithmetic Logic Units (ALUs) • Embedded Processors • Hardcore (dedicated processors) • Dedicated program and data memories • Programmable RAM in FPGA can be used in conjunction with the processor to provide program and data memories • Soft core (synthesized from a HDL) S.Bibin Sam Paul, IEEE Student Branch NIT-T

28. How to Reconfigure FPGA • Logic block functions and interconnections are specified using Hardware Description Language (HDL). • The HDL code is synthesized, mapped, placed ,routed and download onto the chip by vendor-provided tools S.Bibin Sam Paul, IEEE Student Branch NIT-T

29. Xilinx Virtex-5 FPGAs Virtex -5 Development board S.Bibin Sam Paul, IEEE Student Branch NIT-T

30. Xilinx Virtex-5 CLBs • A single CLB in Virtex-5 consists of two slices: SLICEL (logic) and SLICEM (memory). • Each CLB is connected to a switch matrix which can access to a general routing (global) matrix. • Every slice contains four LUTS, wide function MUXs, carry logic, and configurable memory elements. • SLICEM support storing data using distributed RAM and data shifting with 32-bit shift registers S.Bibin Sam Paul, IEEE Student Branch NIT-T

31. Xilinx Virtex-5 Slices SLICE Architecture SLICEL SLICEM S.Bibin Sam Paul, IEEE Student Branch NIT-T

32. Interconnection architecture • Switch box topology S.Bibin Sam Paul, IEEE Student Branch NIT-T

33. Interconnection architecture • Interconnection patterns S.Bibin Sam Paul, IEEE Student Branch NIT-T

34. Which takes more chip area, logic or interconnects? • Logic: 20% ~ 30% • Interconnect: 70% ~ 80% S.Bibin Sam Paul, IEEE Student Branch NIT-T

35. FPGA Resource Comparison S.Bibin Sam Paul, IEEE Student Branch NIT-T

36. Introduction to ASIC Design S.Bibin Sam Paul, IEEE Student Branch NIT-T

37. ASIC Design Flow S.Bibin Sam Paul, IEEE Student Branch NIT-T

38. Industry Standard Multi-Vendor Tools S.Bibin Sam Paul, IEEE Student Branch NIT-T

39. ASIC Back End Flow • Floor Planning • IO Planning • Power Planning • Macro Planning • Placement • Clock Tree Synthesis • Routing • Static Timing Analysis • Physical verification • Chip Finishing • Packaging S.Bibin Sam Paul, IEEE Student Branch NIT-T

40. Floor Plan • Floor planning is the task of deciding how the chip area is to be utilized Floor planning of Core IO Plan Std. Cells Floor planning of Power IP Block Pads S.Bibin Sam Paul, IEEE Student Branch NIT-T

41. Placement • Placement decides the positions of components within allocated blocks • Timing driven P&R is the state of the art • Gates, flip-flops/latches are the common placement objects. • – Smaller elements like logic gates are placed in single row. • – Larger blocks are placed in multiple-rows. S.Bibin Sam Paul, IEEE Student Branch NIT-T

42. Clock Tree Synthesis The Clock Tree or clock distribution network distributes the clock signal(s) from a common point to all the elements that need it S.Bibin Sam Paul, IEEE Student Branch NIT-T

43. Routing • Routing is the process of building the physical connections between blocks as defined by the logical connections. S.Bibin Sam Paul, IEEE Student Branch NIT-T

44. Routing Global Routing – Assigns wires to channels defined during the floor planning phase Detailed Routing – Assigns nets to individual tracks in the channel S.Bibin Sam Paul, IEEE Student Branch NIT-T

45. Static Timing Analysis • Design is broken down into sets of timing paths • All path delays are checked to see if timing constraints have been met in terms of set-up time, Hold time e.t.c S.Bibin Sam Paul, IEEE Student Branch NIT-T

46. Physical Verification DRC – Design Rule Checking LVS – Layout vs. Schematic verifications S.Bibin Sam Paul, IEEE Student Branch NIT-T

47. Chip Finishing Tiling - dummy fill/pattern fill Seal ring Adding Seal-ring tiles S.Bibin Sam Paul, IEEE Student Branch NIT-T

48. Package Fitting Route pads to pins S.Bibin Sam Paul, IEEE Student Branch NIT-T

49. Speech Recognition-Feature Extraction Chip S.Bibin Sam Paul, IEEE Student Branch NIT-T

50. HDL Design S.Bibin Sam Paul, IEEE Student Branch NIT-T