IPHC-LBNL Phone Conference News and PXL sensor (Ultimate) testing at LBNL

1. IPHC-LBNL Phone Conference News and PXL sensor (Ultimate) testing at LBNL

2. PXL Project News • Preparation for CD-2/3 review at BNL in July • Primarily a cost and schedule review but with some technical content. • Releases construction funding. • A set of documentation for the PXL detector is available at http://rnc.lbl.gov/hft/hardware/docs/sensor_review/summary_v2.doc • New Virtex-6 based RDO system boards design. • Design in progress • 3 PCB architecture, new connectors, cables, 9U VME physical format. • Details at http://rnc.lbl.gov/hft/hardware/docs/ultimate/V6_RDO_MB_design_plans_hw_meeting.pptx • Expected to be completed and ready to test in July. • Significant Progress in mechanical structures. • See pictures next slide

3. PXL Mechanical Construction http://rnc.lbl.gov/hft/hardware/docs/ultimate/HFT_Mechanics_20110428.pptx

4. Ultimate Sensor Testing • 5 Sensors mounted to individual test boards. • 2 loaded with digital outputs only. • 3 loaded with digital outputs + analog output buffering.

5. Ultimate Sensor Testing • Testing plan • Power-on tests • Functional testing • Characterization • Status • We have done power on testing and are beginning functional testing. More on this on the next slide. • JTAG is working and we can configure all registers. • More to come.

6. Power-on observations Ultimate un-configured current draw. VDDA ~ 360 mA (E-4), 370 mA (A-2) After RSTB => GND. VDDA ~ 0mA Power on sequence dependent: (RSTB tied to VDDA) Sequence: pwr-on VDDA ~ 490 mA, pwr-on VDDD ~ 620 mA This is a surprise since Phase-1 did not exhibit this behavior. Previous agreement to tie RSTB to VDDD to eliminate the need for this trace on the crowded readout cable. This current draw is not immediately compatible with the current plan for no startup sequence LU protected power supplies for the ladder.

7. Quick architecture review i/o USB ADC SIU FPGA DAQ RDO PCs SRAM Power Supplies Control PCs Trigger Ladder x 4 RDO board x 1 fiber Unified Development Platform Sensor testing Probe testing LU prot. power Black – cfg, ctl, clk. path Blue – data path Red – power / gnd path Green – testing path MTB x 1

8. Power-on current draw 2 possible solutions with many variants: • RSTB Bus on cable: • Control from FPGA – startup sequence control • RC timer circuit on cable (or MTB) – no startup sequence control required • RSTB a “known sensitive” line? • RSTB pad bonded to (any) power bus: • Bonded to VCCA – startup sequence control required. Activate or reset LU-PS Note that either is inherently safe as the LU protection limits current available to the sensors.

9. Summary • For LBNL the testing of the PXL sensor has just begun and we will be moving to functional testing next. • Power-on high current draw can be solved in a variety of ways – we will select one and incorporate it into the design. • We are very interested in knowing if there are any known operational issues, variations from the manual, or hints for operation that IPHC has already discovered. This will help a lot with our testing.