CDA 5155

1. Out-of-order execution: Scoreboarding and Tomasulo Week 2 CDA 5155

2. A more realistic pipeline

3. Dependencies Read after Write (RAW): true dependency add 1 2 3 ; nand 3 4 5 Write after Read (WAR): Anti-dependency add 1 2 3 ; nand 5 6 2 Write after Write (WAW): output dependency add 1 2 3 ; nand 5 6 3 Read after Read (RAR): usually not a problem add 1 2 3 ; nand 1 5 6

4. Out-of-order execution: Variable latencies make out-of-order execution desirable How do we prevent WAR and WAW hazards? How do we deal with variable latency? Forwarding for RAW hazards harder. Instruction add 1 2 3 mul 4 5 6 div 678 add 1 2 7 sub 1 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 IF ID EX M WB IF ID E1 E2 E3 E4 E5 E6 E7 M WB IF ID x x x x x x E1 E2 E3 E4 … IF ID EX M WB IF ID EX M WB

5. CDC 6600

6. Scoreboard: a bookkeeping technique Out-of-order execution divides ID stage: 1. Issue—decode instructions, check for structural hazards 2. Read operands—wait until no data hazards, then read operands Scoreboards date to CDC6600 in 1963 Instructions execute whenever not dependent on previous instructions and no hazards. CDC 6600: In order issue, out-of-order execution, out-of-order commit (or completion) No forwarding! Imprecise interrupt/exception model

7. Scoreboard Architecture(CDC 6600) FP Mult FP Mult FP Divide FP Add Integer Registers Functional Units SCOREBOARD Memory Fetch/Issue

8. Scoreboard Implications Out-of-order completion => WAR, WAW hazards? Solutions for WAR: Stall writeback until all prior uses of the destination register have been read Read registers only during Read Operands stage Solution for WAW: Detect hazard and stall issue of new instruction until other instruction completes Need to have multiple instructions in execution phase => multiple execution units or pipelined execution units Scoreboard keeps track of dependencies between instructions that have already issued. Scoreboard replaces ID, EX, M and WB with 4 stages

9. Four Stages of Scoreboard Control Issue—decode instructions & check for structural hazards (ID1) Instructions issued in program order (for hazard checking) Don’t issue if structural hazard Don’t issue if instruction is output dependent on any previously issued but uncompleted instruction (no WAW hazards) Read operands—wait until no data hazards, then read operands (ID2) All real dependencies (RAW hazards) resolved in this stage, since we wait for instructions to write back data. No forwarding of data in this model!

10. Four Stages of Scoreboard Control Execution—operate on operands (EX) The functional unit begins execution upon receiving operands. When the result is ready, it notifies the scoreboard that it has completed execution. This includes memory ops. Write result—finish execution (WB) Stall until no WAR hazards with previous instructions:Example: DIV 1 2 3 ADD 3 4 5 NAND 6 7 4CDC 6600 scoreboard would stall NAND until ADD reads operands

11. Three Parts of the Scoreboard Instruction status:Which state the instruction is in Functional unit status:—Indicates the state of the functional unit (FU). 9 fields for each functional unit Busy: Indicates whether the pipeline unit is busy or not Op: Operation to perform in the unit (e.g., + or –) Fi: Destination register (for writeback and WAW check) Fj,Fk: Source-register numbers (for reg read and WAR check) Qj,Qk: Functional units producing source registers Fj, Fk (wake up) Rj,Rk: Flags indicating when Fj, Fk are ready (and when already read) Register result status:—Indicates which functional unit will write each register, if one exists. Blank when no pending instructions will write that register

12. Scoreboard Example

13. Detailed Scoreboard Pipeline Control Instruction status Wait until Bookkeeping Issue Not busy (FU) and not result(D) Busy(FU) yes; Op(FU) op; Fi(FU) `D’; Fj(FU) `S1’; Fk(FU) `S2’; Qj Result(‘S1’); Qk Result(`S2’); Rj not Qj; Rk not Qk; Result(‘D’) FU; Read operands Rj and Rk Rj No; Rk No Execution complete Functional unit done Write result f((Fj(f)Fi(FU) or Rj(f)=No) & (Fk(f)Fi(FU) or Rk( f )=No)) f(if Qj(f)=FU then Rj(f) Yes);f(if Qk(f)=FU then Rj(f) Yes);Result(Fi(FU)) 0;Busy(FU) No Pipeline available and no WAW possible Both src operands are available no WAR hazard (no earlier instr has yet to read the dest reg to be written)

14. Scoreboard Example: Cycle 1

15. Scoreboard Example: Cycle 2 • Issue 2nd LD? No Integer pipeline is busy.

16. Scoreboard Example: Cycle 3 • Issue MULT? No, still trying to issue LD

17. Scoreboard Example: Cycle 4 0

18. Scoreboard Example: Cycle 5

19. Scoreboard Example: Cycle 6 • Issue MULT? Yes, but cant read F2 until LD completes.

20. Scoreboard Example: Cycle 7 • Read multiply operands? No, F2 is not ready

21. Scoreboard Example: Cycle 8a(First half of clock cycle) • LD completes. Update Multd and subdwaiting on F2

22. Scoreboard Example: Cycle 8b(Second half of clock cycle)

23. Scoreboard Example: Cycle 9 Note Remaining • Read operands for MULT & SUB? yes • Issue ADDD? No, add pipline busy

24. Scoreboard Example: Cycle 10

25. Scoreboard Example: Cycle 11

26. Scoreboard Example: Cycle 12 • Read operands for DIVD? No, F0 is not available

27. Scoreboard Example: Cycle 13

28. Scoreboard Example: Cycle 14

29. Scoreboard Example: Cycle 15

30. Scoreboard Example: Cycle 16

31. Scoreboard Example: Cycle 17 WAR Hazard! • Why not write result of ADD???

32. Scoreboard Example: Cycle 18

33. Scoreboard Example: Cycle 19

34. Scoreboard Example: Cycle 20

35. Scoreboard Example: Cycle 21 no no • WAR Hazard is now gone... Complete the add

36. Scoreboard Example: Cycle 22

37. …

38. Scoreboard Example: Cycle 61

39. Scoreboard Example: Cycle 62

40. Scoreboard Example: Cycle 62 • In-order issue; out-of-order execute & commit

41. CDC 6600 Scoreboard Historical context: Speedup 1.7 from compiler; 2.5 by hand BUT slow memory (no cache) limits benefit Limitations of 6600 scoreboard: No forwarding hardware Limited to instructions in basic block (small window) Small number of functional units (structural hazards), especially integer/load store units Do not issue on structural hazards Wait for WAR hazards Prevent WAW hazards Precise interrupts?

42. IBM 360/91

43. Another Dynamic Algorithm: Tomasulo’s Algorithm For IBM 360/91 about 3 years after CDC 6600 (1966) Goal: High Performance without special compilers Differences between IBM 360 & CDC 6600 ISA IBM has only 2 register specifiers/instr vs. 3 in CDC 6600 IBM has 4 FP registers vs. 8 in CDC 6600 IBM has memory-register ops Small number of floating point registers prevented interesting compiler scheduling of operations This led Tomasulo to try to figure out how to get more effective registers — renaming in hardware! Why Study? The descendants of this have flourished! Alpha 21264, HP 8000, MIPS 10000, Pentium II, PowerPC 604, …

44. Tomasulo Algorithm vs. Scoreboard Control & buffers distributed with Function Units (FU) vs. centralized in scoreboard; FU buffers called “reservation stations”; have pending operands Registers in instructions replaced by values or pointers to reservation stations(RS); called registerrenaming; avoids WAR, WAW hazards More reservation stations than registers, so can do optimizations compilers can’t Results to FU from RS, not through registers, over Common Data Bus that broadcasts results to all FUs Load and Stores treated as FUs with RSs as well Integer instructions can go past branches, allowing FP ops beyond basic block in FP queue

45. Tomasulo Organization FP Registers From Mem FP Op Queue Load Buffers Load1 Load2 Load3 Load4 Load5 Load6 Store Buffers Add1 Add2 Add3 Mult1 Mult2 Reservation Stations To Mem FP adders FP multipliers Common Data Bus (CDB)

46. Reservation Station Components Op: Operation to perform in the unit (e.g., + or –) Vj, Vk: Value of Source operands Store buffers has V field, result to be stored Qj, Qk: Reservation stations producing source registers (value to be written) Note: No ready flags as in Scoreboard; Qj,Qk=0 => ready Store buffers only have Qi for RS producing result Busy: Indicates reservation station or FU is busy Register result status—Indicates which functional unit will write each register, if one exists. Blank when no pending instructions that will write that register.

47. Three Stages of Tomasulo Algorithm 1. Issue—get instruction from FP Op Queue If reservation station free (no structural hazard), control issues instr & sends operands (renames registers). 2. Execute—operate on operands (EX) When both operands ready then execute; if not ready, watch Common Data Bus for result 3. Write result—finish execution (WB) Write on Common Data Bus to all awaiting units; mark reservation station available Normal data bus: data + destination (“go to” bus) Common data bus: data + source (“come from” bus) 64 bits of data + 4 bits of Functional Unit source address Write if matches expected Functional Unit (produces result) Does the broadcast

48. Tomasulo Example

49. Tomasulo Example Cycle 1

50. Tomasulo Example Cycle 2 Note: Unlike 6600, can have multiple loads outstanding (This was not an inherent limitation of scoreboarding)