:: 4 ¾ :: Assembly Language (Re-CAP)

1. :: 4 ¾ :: Assembly Language (Re-CAP)

2. Observations • Instruction Cycleis defined as the time required to complete the execution of an instruction • Machine Cycleis defined as the time required to complete one operation of accessing memory, I/O, or acknowledging external request • T-Stateis defined as one subdivision of the operation performed in one clock period

3. Time Delay with registers • Using one register MVI C,FFH (7T) LOOP: DCR C (4T) JNZ LOOP (7/10T) • Using a register pair LXI B,2384H (10T) LOOP: DCX B (6T) MOV A,C (4T) ORA B (4T) JNZ LOOP (7/10T)

4. Time Delay with registers • Write a program to count in hexadecimal from FFH to 00H in a system with 0.5μs clock period. • Use register C to setup 1ms delay between each count and display the numbers at an output port • The delay program will be MVI C,FFH (7T) DELAY: DCR C (4T) JNZ DELAY (7/10T)

5. MVI C,FFH (7T) • DELAY: DCR C (4T) • JNZ DELAY (7/10T) Calculate the Time Delay • Given clock frequency of the system = 2MHz • Clock frequency, f = 2 MHz • Clock period, T = 1/f T = 1/(2 * 106) T = 0.5 μs • Time delay outside loop • Time to execute MVI = 7 T-states * 0.5 μs MVI = 3.5 μs • FFH equal to 25510 • Instruction DCR and JNZ form a loop with a total of 14 T-states • The loop will repeated 255 times until reg C = 0

6. MVI C,FFH (7T) • DELAY: DCR C (4T) • JNZ DELAY (7/10T) Calculate the Time Delay • Time delay in loop: TL = T * total loop T-states * counter TL = 0.5 μs * 14 * 255 TL = (0.5 * 10-6 * 14 * 255) TL = 1785 μs TL ≈ 1.8 ms • When counter = 0, the JNZ T-states will become 7 T-states, so we need to adjust loop delay. TA = (10 – 7) * Clock period TA = 3 * 0.5 μs TA = 1.5 μs Time delay in loop after adjustment : TLA = TL – TA TLA = 1785 μs – 1.5 μs TLA = 1783.5 μs

7. MVI C,FFH (7T) • DELAY: DCR C (4T) • JNZ DELAY (7/10T) Calculate the Time Delay • So the total delay will be.. . Total delay = TD = TO + TLA TD = (7 T-states * 0.5 μs) + 1783.5 μs TD = 1787 μs TD ≈ 1.8 ms • The time delay can be varied by changing the counter, FFH Time delay outside loop • Time delay in loop • after adjustment +

8. 8085

9. 8085 Demultiplexed Address and Data Bus withControl Signals

10. 8085 Demultiplexed Address and Data Bus withControl Signals • The 8085 microprocessor has a status signal IO/M and two control signals RD and WR. • Four control signals can be generated MEMR, MEMW, IOR, and IOW • The 8085 microprocessor transfers data from memory to the microprocessor by using the control signal MEMR • The 8085 microprocessor transfers data from the microprocessor to the memory by using the control signal MEMW • The 8085 microprocessor accepts data from input devices by using the control signal IOR and sends data to output devices by using IOW

11. Example • Assume that the accumulator contains data byte 82H, and the instruction MOV C,A is fetched (4FH), the steps in decoding and executing the instruction will be: • The microprocessor places the contents of the data bus (4FH) on the instruction register and decodes the instruction • Transfers the contents of the accumulator (82H) to the temporary register in the ALU • Transfers the contents of the temporary register to register C

12. F R R W 3 3 = 13 4 3 Machine cycle • In each instruction cycle, the first operation is Opcode Fetch, and this cycle can be 4 to 6 T-states duration. • Others, use 3T-states duration • Machine cycle types: • FFour clock period instruction fetch • S Six clock period instruction fetch • R Memory read • I I/O read • W Memory write • O I/O write

13. Instruction Cycles, Machine Cycles and T-states • The complete fetchingand execution of one instruction is called an instruction cycle. • An instruction cycle comprises one or more machine cycles. • A machine cycle is a basic operation the processor can perform. • Each machine cycle takes a minimum of 3 to a maximum of 6processor reference clock cycles. • In this context a processor clock cycle is called a T-state remember this slide?

14. Example of an Instruction Cycle • Example Instruction : STA addr16 remember this slide?

15. How to Recognize Machine Cycles 1. 1st machine cycle, the 8085 places the address (2000H) on the address bus and fetches the opcode (32H) 2. 2nd machine cycle is Memory Read the processor places the address (2001H) and gets the low-order byte (65H) 3. 3rd machine cycle is Memory Read the processor places the address (2002H) and gets the high-order address (20H) 4. The last machine cycle is Memory Write. The 8085 places the address (2065H) on the address bus, identifies the operation as Memory Write, it places thecontent of the accumulator on the data bus and asserts the WR signal. During the last T-state, the contents of data bus are placed in memory location (2065H)

16. 8255 Port Declaration

17. Declaring I/O & O/P METHOD 1 PORTA:EQU 80H; PORTB:EQU 81H; PORTC: EQU 82H; CTRLPORT: EQU 83H; MVI A, 90H; OUT CTRLPORT; “OR I CAN PROGRAM IT LIKE THIS SINCE SOME SIMULATION SOFTWARES ALREADY UNDERSTANDS THE PORT CONDITION” METHOD 2 MVI A, 10010000B; OUT 83H;

18. BLINKING LED Figure below shows the connection between LED and switch with 8255 I/O port. Write a program to make the LED blink when the switch is ON and stop blinking when the switch is OFF.

19. EXAMPLE QUESTION FOR MINI PROJECT • By applying the Intel 8085 microprocessor, recommend and develop a suitable program for the UPS system shown in the figure below. The conditions of LEDs are shown in Table 1. Assume that switches are used at Port B as the input indicating the percentage of the remaining Power of the UPS. A Turn on Switch for the UPS system is connected to PC0.

21. QUESTION 1 • Write a program that counts the number of winners in a lottery contest. The total number of contestants are 5 people. The contestants lottery numbers are stored beginning from 2020H. Lottery numbers are based on 4 bit binary numbers. The winning number is 1111B. The number of winners should be in the E register.

22. Basic Flow Chart • Declare DATA for contestant numbers at memory addressing location at HL pair. • Load the winning number. • Compare winning number with contestant number. If it hits the jackpot go to another subroutine. ……. U guys are engineers. Figure out the rest!!!!

23. Question 2 • Evaluate the average SiO2 (oxide thickness) on a silicon substrate. There are 5 measurements which have been carried out at each subtrate location. Assume that the oxide thickness value is in Decimal and has been stored beginning in Memory Location 2020H. Store the average in register A and its remainder in register E.

24. Any questions?