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Multivibrator Circuits

Multivibrator Circuits. Bistable Multivibrator (Flip-Flops) Astable Multivibrator (Clocks or Oscillators) Schmitt-Trigger Inverter (7414) 555 Timer Crystal Oscillator Monostable Multivibrator (One-Shots) Non-Retriggerable (74121) Retriggerable (74123) VHDL Coding.

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Multivibrator Circuits

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  1. Multivibrator Circuits • Bistable Multivibrator (Flip-Flops) • Astable Multivibrator (Clocks or Oscillators) • Schmitt-Trigger Inverter (7414) • 555 Timer • Crystal Oscillator • Monostable Multivibrator (One-Shots) • Non-Retriggerable (74121) • Retriggerable (74123) • VHDL Coding ECE 3450 M. A. Jupina, VU, 2010

  2. Some Key Lecture Objectives • To learn how timing signals are generated at low frequencies (< 1 MHz) and high frequencies (>1 MHz). • To learn how clock and pulse signals are generated either through the use of ICs or VHDL coding. • To gain a better understanding of how to apply timing signals in a digital design. ECE 3450 M. A. Jupina, VU, 2010

  3. Schmitt-Trigger Inverter (a) If input transition times are too long, a standard logic device-output might oscillate or change erratically; (b) a logic device with a Schmitt-trigger type of input will produce clean, fast output transitions. ECE 3450 M. A. Jupina, VU, 2010

  4. VOUT VOH VOL VIN VTL VTH Schmitt-Trigger Inverter Operation • As VIN increases, VOUT = VOH until VIN > VTH • then VOUT = VOL • When VIN begins to decrease, VOUT = VOL until VIN < VTL • then VOUT = VOH ECE 3450 M. A. Jupina, VU, 2010

  5. Schmitt-Trigger Oscillator IIN ECE 3450 M. A. Jupina, VU, 2010

  6. Analysis of a Schmitt-Trigger Oscillator VC(t) VTH VTL t t VOH VOUT(t) VOL TL TH t = 0 t = 0' Assume Iin = 0, thus IR(t) = IC(t) Capacitor Charging Capacitor Discharging VC(t) VC(t) VOL VOH ECE 3450 M. A. Jupina, VU, 2010

  7. Analysis of a Schmitt-Trigger OscillatorContinued Capacitor Discharging Capacitor Charging ECE 3450 M. A. Jupina, VU, 2010

  8. Example: Show how to use a 74LS14 Schmitt-trigger inverter to produce an approximate square wave with a frequency of 10 KHz. Solution: ECE 3450 M. A. Jupina, VU, 2010

  9. PSPICE Simulation of a Schmitt-Trigger Oscillator (7414) ECE 3450 M. A. Jupina, VU, 2010

  10. 555 Timer as an Astable Multivibrator 1 – Ground 5 – FM Input (Tie to gnd via bypass cap) 2 – Trigger 6 – Threshold 3 – Output 7 – Discharge 4 – Reset (Set HIGH for normal operation) 8 – Voltage Supply (+5 to +15 V) ECE 3450 M. A. Jupina, VU, 2010

  11. Block Diagram of a 555 Timer Configured as an Oscillator ECE 3450 M. A. Jupina, VU, 2010

  12. 555 Timer Block Diagram Contents • Resistive voltage divider (equal resistors) sets threshold voltages for comparators V1 = VTH = 2/3 VCC V2 = VTL = 1/3 VCC • Two Voltage Comparators • For A1, if V+ > VTH then R =HIGH • For A2, if V- < VTL then S = HIGH • RS FF • If S = HIGH, then FF is SET, = LOW, Q1 OFF, VOUT = HIGH • If R = HIGH, then FF is RESET, = HIGH, Q1 ON, VOUT = LOW • Transistor Q1 is used as a Switch ECE 3450 M. A. Jupina, VU, 2010

  13. Timing Diagram of a 555 Oscillator 1 2 3 VC(t) VTH VTL t VCC VOUT(t) TL TH t t = 0 t = 0' ECE 3450 M. A. Jupina, VU, 2010

  14. Operation of a 555 Oscillator • Assume initially that the capacitor is discharged. • For A1, V+ = VC = 0V and for A2, V- = VC = 0V, so R=LOW, S=HIGH, = LOW , Q1 OFF, VOUT = VCC • Now as the capacitor charges through RA & RB, eventually VC > VTL so R=LOW & S=LOW. FF does not change state. RA RB VC(t) VCC ECE 3450 M. A. Jupina, VU, 2010

  15. Operation of a 555 OscillatorContinued • Once VC VTH • R=HIGH, S=LOW, = HIGH ,Q1 ON, VOUT = 0 • Capacitor is now discharging through RB and Q1 to ground. • Meanwhile at FF, R=LOW & S=LOW since VC < VTH. RB VC(t) Q1 ECE 3450 M. A. Jupina, VU, 2010

  16. Operation of a 555 OscillatorContinued • Once VC < VTL • R=LOW, S=HIGH, = LOW , Q1 OFF, VOUT = VCC • Capacitor is now charging through RA & RB again. RA RB VC(t) VCC ECE 3450 M. A. Jupina, VU, 2010

  17. Analysis of a 555 Oscillator Capacitor Discharging Capacitor Charging ECE 3450 M. A. Jupina, VU, 2010

  18. Example: Design a 555 Oscillator to produce an approximate square-wave at 40 KHz. Let C > 470 pF. Examples One Possible Solution: F=40KHz; T=25µs; t1=t2=12.5µs For a square-wave RA<<RB; Let RA=1K and RB=10K t1=0.693(RB)(C); 12.5µs=0.693(10K)(C); C=1800pF T=0.693(RA+2RB)C: T=0.693(1K+20K)1800pF T=26.2µs; F=1/T; F=38KHz (almost square-wave). Example: A 555 oscillator can be combined with a J-K FF to produce a 50% duty-cycle signal. Modify the above circuit to achieve a 50% duty-cycle, 40 KHz signal. One Possible Solution: Reduce by half the 1800pF. This will create a T=13.1µs or F=76.35 KHz (almost square-wave). Now, take the output of the 555 Timer and connect it to the CLK input of a J-K FF wired in the toggle mode (J and K inputs connected to +5V). The result at the Q output of the J-K FF is a perfect 38.17 KHz square-wave. ECE 3450 M. A. Jupina, VU, 2010

  19. Problem 10.24 - The 555 Programmable Timer Chip 5 V 4 8 R a 3 7 Clock 555 (output) R b Timer 2 6 C 1 1 5 m 0.01 F (a) For 50% duty cycle and 500 KHz frequency, C1= 100 pF, then Ra= 1 kΩ and Rb= 14 kΩ (b) For 75% duty cycle and 500 KHz frequency, C1= 1000 pF, then Ra= 1.42 kΩ and Rb= 0.71 kΩ ECE 3450 M. A. Jupina, VU, 2010

  20. PSPICE Simulation of a 555 Oscillator R1=R2, duty cycle = 66% and f =16 KHz ECE 3450 M. A. Jupina, VU, 2010

  21. Crystal Oscillator • An oscillator circuit that uses a piezoelectric crystal. • Piezoelectric materials support an exchange of energy between mechanical compression and applied electric field. • If a potential is applied between the electrodes, forces will be exerted on the bound charges within the crystal. Deformations take place within the crystal and an electromechanical system is formed which will vibrate when properly excited. ECE 3450 M. A. Jupina, VU, 2010

  22. Crystal Oscillator, Continued • The oscillation frequency (10 KHz – 80 MHz) is very precisely determined by the physical dimensions of the crystal. • High Q (1000 – 10,000) resonators are usually built using quartz single crystal or ceramic materials. • These resonators are extremely stable (ppm’s) with respect to time and temperature. • To generate clock frequencies into the GHz range, DPLL (Digital Phase Lock Loops) are used for frequency multiplication. fo XTAL OSC DPLL N•fo ECE 3450 M. A. Jupina, VU, 2010

  23. Crystal Oscillator Circuit Example crystal oscillator symbol and equivalent circuit Pierce oscillator circuit equivalent circuit of Pierce oscillator ECE 3450 M. A. Jupina, VU, 2010

  24. Example: 50 MHz Oscillator on the Altera DE2 Board ECE 3450 M. A. Jupina, VU, 2010

  25. Clock Divider ECE 3450 M. A. Jupina, VU, 2010

  26. Non-Retriggerable One-Shot (OS) ECE 3450 M. A. Jupina, VU, 2010

  27. Comparison of Non-Retriggerable and Retriggerable OS responses for tPULSE = 2 ms ECE 3450 M. A. Jupina, VU, 2010

  28. Example: Refer to the waveforms in (a) on previous page. Change the OS pulse duration to 0.5 ms and determine the Q output for both types of OS. Then repeat using a pulse duration of 1.5 ms. Example Solution: ECE 3450 M. A. Jupina, VU, 2010

  29. 74121 Non-Retriggerable OS ECE 3450 M. A. Jupina, VU, 2010

  30. Example: (a) Show how a 74121 can be connected to produce a negative-going pulse with a 5 ms duration whenever A1 or A2 is connected to a negative-going trigger. (b) Modify the circuit so that when a signal “G” goes low it can be used to disable the 74121. Example Solution: ECE 3450 M. A. Jupina, VU, 2010

  31. tw = 0.33 RT Cext 74123 Dual One Shot PSPICE Simulation ECE 3450 M. A. Jupina, VU, 2010

  32. VHDL Nonretriggerable One-Shot ECE 3450 M. A. Jupina, VU, 2010

  33. Simulation of the Nonretriggerable One-Shots Comparison of this VHDL OS to an IC OS • VHDL OS output does not change state until a rising edge clock signal occurs whereas an IC OS output changes “immediately” when triggered. • The trigger signal for the VHDL OS must be active during a rising clock edge so as to be recognized (the IC OS trigger is an asynchronous signal, i.e., it can occur whenever). • The VHDL OS is level-triggered whereas the IC OS is edge-triggered. ECE 3450 M. A. Jupina, VU, 2010

  34. Detecting Edges ECE 3450 M. A. Jupina, VU, 2010

  35. VHDL Retriggerable One-Shot with Edge Trigger ECE 3450 M. A. Jupina, VU, 2010

  36. Simulation of the Edge-Triggered Retriggerable One-Shot • Comparison to Previous VHDL OS • Just as the case before, the output of this OS does not change state until a rising edge clock signal occurs. • Unlike the previous OS, this OS is edge-triggered. • Just as the case before, the trigger signal for this OS must be active during a rising clock edge so as to be recognized. ECE 3450 M. A. Jupina, VU, 2010

  37. Final Notes on VHDL OS • To minimize the effects of a delayed output pulse with respect to a rising edge trigger, the clock frequency and the initial value of the count can be increased so that an output pulse of the same width is produced. • An asynchronously triggered OS can be created in VHDL but the output pulse generated will fluctuate in width by up to one clock period. ECE 3450 M. A. Jupina, VU, 2010

  38. trigger (10 KHz) clock (100 KHz) Q1 Example of a Dual One Shot Circuit ECE 3450 M. A. Jupina, VU, 2010

  39. -- retriggerable edge-triggered one-shot -- time delay = delay * clock period LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; USE IEEE.STD_LOGIC_ARITH.all; USE IEEE.STD_LOGIC_UNSIGNED.all; ENTITY os1 IS PORT ( clock, trigger, reset : IN BIT; delay : IN INTEGER RANGE 0 TO 15; q : OUT BIT); END os1; ARCHITECTURE a OF os1 IS BEGIN PROCESS (clock, reset) VARIABLE count : INTEGER RANGE 0 TO 15; VARIABLE trig_was : BIT; BEGIN IF reset = '0' THEN count := 0; ELSIF (clock'EVENT AND clock = '0' ) THEN IF trigger = '0' AND trig_was = '1' THEN count := delay; -- load counter trig_was := '0'; -- "remember" edge detected ELSIF count = 0 THEN count := 0; -- hold @ 0 ELSE count := count - 1; -- decrement END IF; IF trigger = '1' THEN trig_was := '1'; END IF; END IF; IF count /= 0 THEN q <= '1'; ELSE q <= '0'; END IF; END PROCESS; END a; OS1 VHDL ECE 3450 M. A. Jupina, VU, 2010

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