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Unit 11 Latches and Flip-Flops

Unit 11 Latches and Flip-Flops. Ku-Yaw Chang canseco@mail.dyu.edu.tw Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh University. Outline. 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop

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Unit 11 Latches and Flip-Flops

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  1. Unit 11Latches and Flip-Flops Ku-Yaw Chang canseco@mail.dyu.edu.tw Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh University

  2. Outline 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop 11.6 J-K Flip-Flop 11.7 T Flip-Flop 11.8 Flip-Flops with Additional Inputs 11.9 Summary Latches and Flip-flops

  3. Gated D Latch • Two inputs • A data input (D) • A gate input (G) • Constructed from an S-R latch and gates Latches and Flip-flops

  4. Timing Diagram • G = 1 • The Q output follows the D input. • Transparent latch • G = 0 • The Q output holds the last value of D (no state change) Latches and Flip-flops

  5. Symbol and Truth Table Latches and Flip-flops

  6. Outline 11.1 Introduction 11.2 Set-Reset Latch 11.3 Gated D Latch 11.4 Edge-Triggered D Flip-Flop 11.5 S-R Flip-Flop 11.6 J-K Flip-Flop 11.7 T Flip-Flop 11.8 Flip-Flops with Additional Inputs 11.9 Summary Latches and Flip-flops

  7. D Flip-Flop • Two inputs • D (data) • The output changes only in response to the clock, not to a change in D. • Ck (clock) Latches and Flip-flops

  8. D Flip-Flop • The output can change in response to a 0 to 1 transition on the clock input • Triggered on the rising edge (or positive edge) • The output can change in response to a 1 to 0 transition on the clock input • Triggered on the falling edge (or negative edge) • Active edge • The clock edge (rising or falling) that triggers the flip-flop Latches and Flip-flops

  9. D Flip-Flop • The state after the active clock edge (Q+) is equal to the input (D) before the active edge. • Characteristic equation : Q+ = D Latches and Flip-flops

  10. D Flip-Flop • The output change are delayed • Falling edge trigger Latches and Flip-flops

  11. D Flip-Flop • A rising-edge-triggered D flip-flop • two gated D latches • an inverter Latches and Flip-flops

  12. D Flip-Flop Time Analysis Latches and Flip-flops

  13. Setup and Hold Times • Propagation delay is the time between • the active edge of the clock • the resulting change in the output • If D changes at the same time as the active edge, the behavior is unpredictable. • Setup time (tsu) • the amount of time that D must be stable before the active edge • Hold time (th) • the amount of time that D must hold the same value after the active edge Latches and Flip-flops

  14. Setup and Hold Times • The times at which D is allowed to change are shaded in the following timing diagram. Latches and Flip-flops

  15. Determination ofMinimum Clock Period Latches and Flip-flops

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