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The whole design and simulation of a 10-bit ADC with time to digital converter

The whole design and simulation of a 10-bit ADC with time to digital converter. 目录. 一、 ADC 的整体架构. 二、 ADC 整体仿真及结果. 三、 ADC 仿真介绍， FFT 分析、码密度分析. 四、电路设计中遇到的问题与感想. 五、工作展望. 一、 ADC 的整体架构. 2 、 ADC 整体时序. 一、 ADC 的整体架构 ——TDC. 二、 ADC 整体仿真及结果 FFT 分析.

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The whole design and simulation of a 10-bit ADC with time to digital converter

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  1. The whole design and simulation of a 10-bit ADC with time to digital converter

  2. 目录 一、ADC的整体架构 二、ADC整体仿真及结果 三、ADC仿真介绍，FFT分析、码密度分析 四、电路设计中遇到的问题与感想 五、工作展望

  3. 一、ADC的整体架构 2、ADC整体时序

  4. 一、ADC的整体架构——TDC

  5. 二、ADC整体仿真及结果FFT分析 Simulation is done by applying a 5.371KHz input. The 4096-point fast Fourier transform shows a total signal-to-noise-plus-distortion ratio (SNDR) of 55.9483 dB, which provides an ENOB of ((SNDR-1.76)/6.02)=9.001. Output spectrum for a 2.9KHz sinusoid input

  6. 参考文献： • [I] S. Yoshihara et aI., "A 1Il.8-ineh 6.4 MPixel 60 frames/s CMOS Image Sensor With Seamless Mode Change," IEEE J. Solid-State Circuits, vol.4 1, no. 12, Dec. 2006 • [2] Snoeij MF, et aI., "A CMOS image sensor with a column-level multi-ramp single-slope ADC," in ISSCC Dig. Tech. Papers, pp.506-507, 2007. • [3] Lim, S., et aI., "A High-Speed CMOS Image Sensor With Column-Parallel Two-Step Single-Slope ADCs," IEEE Transactions on Electron Devices,vol. 56, issue 3, pp. 393-398, 2009. • [4] Muung Shin, et al,.” Column Parallel Single-Slope ADC with Time to Digital Converter for CMOS Imager” ICECS 2010 , Page(s): 863 - 866 • [5] Min Park,et,al.,” A Single-Slope 80MS/s ADC using Two-Step Time-to-Digital Conversion” ISCAS.2009.5117958 Publication Year: 2009 , Page(s): 1125 - 1128 • [6] Chorng-Sii Hwang,et,al,.” A High-Precision Time-to-Digital Converter Using a Two-Level Conversion Scheme” IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 51, NO. 4, AUGUST 2004 • [7]专利 Jan Bogaerts “ANALOG-TO-DIGITAL CONVERSION IN PIXEL ARRAYS” • [8] Piotr Dudek” A High-Resolution CMOS Time-to-Digital ConverterUtilizing a Vernier Delay Line” IEEE TRANSACTIONS ON SOLID-STATE CIRCUITS, VOL. 35, NO. 2, FEBRUARY 2000 • [9] Kostas Karadamoglou,.” An 11-bit High-Resolution and Adjustable-Range CMOS Time-to-Digital Converter for Space Science Instruments” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 1, JANUARY 2004

  7. [10] Jussi-Pekka Jansson,” A CMOS Time-to-Digital Converter With Better Than 10 ps Single-Shot Precision” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 6, JUNE 2006 • [11] Jianjun Yu,” A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13 􀀀m CMOS Technology” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 4, APRIL 2010 • [12] Ping Lu, Member,” A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 7, JULY 2012 • [13] Zhimin Zhou,Bedabrata PainEric,R. Fossum.CMOS Active Pixel Sensor with On-Chip Successive Approximation Analog-To-Digital Converter[J].IEEE Transactions On Electron Devices,1997,VOL. 44, NO. 10. • [14]Shinichiro Matsuo,Timothy J.Bales,Masahiro Shoda et al. 8.9-Megapixel Video Image Sensor With 14-b Column-Parallel SAR-ADC[J]. IEEE Transactions On Electron Devices,2009,VOL. 56, NO. 11. • [15]Min-Woong Seo, Sung-Ho Suh, Tetsuya Iida et al. A Low-Noise High Intrascene Dynamic Range CMOS Image Sensor With a 13 to 19b Variable-Resolution Column-Parallel Folding-Integration/Cyclic ADC[J]. IEEE Journal Of Solid-State Circuits, 2012,Vol. 47, No. 1.

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