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Verilog Intro: Part 1

Verilog Intro: Part 1. Hardware Design Languages. A Hardware Description Language (HDL) is a language used to describe a digital system, for example, a computer or a component of a computer. A digital system can be described at several levels:

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Verilog Intro: Part 1

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  1. Verilog Intro: Part 1

  2. Hardware Design Languages • A Hardware Description Language (HDL) is a language used to describe a digital system, for example, a computer or a component of a computer. • A digital system can be described at several levels: • Switch level: wires, resistors and transistors • Gate level: logical gates and flip flops • Register Transfer Level (RTL): registers and the transfers of information between registers. • Two Major HDLs in Industry • VHDL • Verilog HDL

  3. Verilog HDL vs. VHDL VHDL • “V” is short for Very High Speed Integrated Circuits. • Designed for and sponsored by US Department of Defense. • Designed by committee (1981-1985). • Syntax based on Ada programming language. • Was made an IEEE Standard in 1987. Verilog HDL (VHDL) • Was introduced in 1985 by Gateway Design System Corporation, now a part of Cadence Design Systems, Inc.'s Systems Division. • Was made an IEEE Standard in 1995 • Syntax based on C programming language.

  4. Design Methodology

  5. Identifiers • An identifier is composed of a space-free sequence of uppercase and lowercase letters from alphabet, digits (0,1,….9), underscore (_), and the $ symbol. • Verilog is a case sensitive language. • c_out_barand C_OUT_BAR are two different identifiers • The name of a variable may not begin with a digit or $, and may be up to 1,024 characters long. • e.g. clock_, state_3

  6. Comments • There are two kinds of comments: single line and multiline. • A single-line comment begins with two forward slashes (//) • A multiline comment begins with the pair of characters /* and terminate with the characters */ • Example: • // This is a single-line comments • /* This is a multiline comments more comments here …………………………………. */

  7. Numbers • Numbers are specified using the following form <size><base format><number> • Size: a decimal number specifies the size of the number in bits. • Base format: is the character ’ followed by one of the following characters • b for binary,d for decimal,o(octal),h(hex). • Number: set of digits to represent the number.

  8. Numbers • Example : x = 347 // decimal number x = 4’b101 // 4- bit binary number 0101 x = 6’o12 // 6-bit octal number x = 16’h87f7 // 16-bit hex number h87f7 x = 2’b101010 x = 2’d83 • String in double quotes “ this is an introduction”

  9. Operators • Bitwise Operators ~ NOT & AND | OR ^ XOR ~| NOR ~& NAND ^~ or ~^ XNOR • Logical & Relational Operators !, &&, | |, ==, !=, >=, <=, >, <

  10. Operators • Arithmetic Operators +, -, *, / , % • Concatenation & Replication Operators {identifier_1, identifier_2, …} {n{identifier}} • Examples: {REG_IN[6:0],Serial_in}, {8 {1’b0}}

  11. Value Logic System • Data type for signals • Bits (value on a wire) • 0, 1 • x unknow value • Vectors of bits (parallel wires or registers) • A[3:0] is a vector of 4 bits: A[3], A[2], A[1], A[0] • Concatenating bits/vectors into a vector • B[7:0] = {A[3], A[3], A[3], A[3], A[3:0]}; • B[7:0] = {3{A[3]}, A[3:0]};

  12. Data Types: Constants • A constant is declared with the keyword parameter in a statement assigning a name and a value to the constant • The value of a constant is fixed during simulation. • Examples: • parameter HIGH_INDEX= 31; // integer • parameter BYTE_SIZE = 8;

  13. Data Types: Variables • Two basic families of data types for variables: Nets and Registers • Net variables – e.g. wire • Variable used simply to connect components together • Usually corresponds to a wire in the circuit. • Register variables – e.g. reg • Variable used to store data as part of a behavioral description • Like variables in ordinary procedural languages • Note: • regshould only be used with always and initial blocks (to be presented …) • The regvariables store the last value that was procedurally assigned to them whereas the wire variables represent physical connections between structural entities such as gates.

  14. Continuous Assignment • A continuous assignment statement is declared with the keyword assign, followed by a net(e.g. type wire) variable, an assignment operator(=), and an expression. • assign corresponds to a connection. • Target is never a regvariable. • assign A = B | (C & ~D); // not the use of ~ not ! • assign B[3:0] = 4'b01XX; • assign C[15:0] = 16'h00ff; //(MSB:LSB) • Assign {Cout, S[3:0]} = A[3:0] + B[3:0] + Cin;

  15. Procedural Assignment & String • Procedural assignments have the form <reg variable> = <expression> • where the <reg variable> must be a register or memory. • e.g. reg enable, d; enable = 0; d = 0;

  16. Primitives • No declaration required (predefined) ; • Can only be instantiated • Example: and a1 (C, A, B); //instance name • Usually better to provide instance name for debugging. • Example: or o1 (SET, ~A, C ), o2(N, ABC,SET ); • Example: and #(10) a2(o, i1, i2); // name + delay

  17. Program Structure: Modules • Any digital system is a set of modules. • Modules may run concurrently, but usually there is one top level module to specify a closed system containing both test data and hardware models. The top level module invokes instances of other modules. • A module is never called, it is instantiated. • Modules can be specified behaviorally or structurally (or a combination of the two). • A behavioral specification defines the behavior of a digital system using traditional programming language constructs (e. g.,if else, assignment statements). • A structural specification expresses the behavior of a digital system (module) as a hierarchical interconnection of submodules.

  18. The Structure of a Module • The structure of a module is the following: module <module name> (<port list>); <declares> <module items> endmodule • <module name> is an identifier that uniquely names the module. • <port list> is a list of input, output and inout ports which are used to connect to other modules. • <declares> specifies data objects as registers, memories & wires as wells as procedural constructs such as functions & tasks. • <module items> may be • initial constructs, • always constructs, • continuous assignments or • instances of modules.

  19. Taste of Verilog module Add_half ( sum, c_out, a, b ); input a, b; output sum, c_out; wire c_out_bar; xor (sum, a, b); nand (c_out_bar, a, b); not (c_out, c_out_bar); endmodule Module name Module ports Declaration of port modes Declaration of internal signal Instantiation of primitive gates Verilog keywords a sum b c_out_bar c_out

  20. Taste of Verilog module Add_half ( sum, c_out, a, b ); input a, b; output sum, c_out; assign {c_out, sum} = a + b; endmodule a sum b c_out_bar c_out

  21. Using Verilogger Pro • An evaluation version is included in a the CD coming with your text book. • Start Verilogger StartProgramSynaptiCadVerilogger Pro..

  22. How to Write a new code • Open any text editor. • Write in your code. • Save the file with .v extension. • Test your code using Verilogger Pro; • Start Verilogger Pro • Right click the project window and select add hdl file • Click the triangular green button from the tools bar to run the code. • If you have any errors you will see them the report window.

  23. Test Bench module <test module name> ; // Data type declaration // Instantiate module ( call the module that isgoing to be tested) // Apply the stimulus // Display results endmodule

  24. Test Bench Example module test_my_nand; // Test bench to test half adder reg A, B; wire s, cOut; Add_half test( s, cOut, A, B ); // instantiate my_NAND. initial begin // apply the stimulus, test data A = 1'b0; B = 1'b0; #100 A = 1'b1; // delay one simulation cycle, then change A=>1. #100 B = 1'b1; #100 A = 1'b0; end initial #500 $finish; initial begin // setup monitoring //$monitor("Time=%0d a=%b b=%b out1=%b", $time, A, B, F); end endmodule

  25. User-Defined Primitives // User defined primitive(UDP) primitive UDP_1 (F,A,B,C); output F; // only one output is allowed input A,B,C; // Truth table for F(A,B,C) = Minterms (0,2,4,6,7) table // A B C : F (Note that this is only a comment) 0 0 0 : 1; 0 0 1 : 0; 0 1 0 : 1; 0 1 1 : 0; 1 0 0 : 1; 1 0 1 : 0; 1 1 0 : 1; 1 1 1 : 1; endtable endprimitive

  26. Procedural Blocks • There are two types of procedural blocks in Verilog. • initial for single-pass behavior : initial blocks execute only once at time zero (start execution at time zero). • always for cyclic behavior: always blocks loop to execute over and over again, in other words as name means, it executes always. • Procedural assignment may only appear in initial and always constructs. • The initial and always constructs are used to model sequential logic. • Continuous statement is used to model combinational logic.

  27. Example: Initial Block module initial_example(); regclk,reset,enable,data; initial begin clk= 0; reset = 0; enable = 0; data = 0; end endmodule The initial block is executed at time 0. Initial block just execute all the statements within begin and end statements.

  28. Control Constructs • Control Constructs • Can be used in the procedural sections of code. • Selection • if statement: if (A == 4) begin B = 2; end else begin B = 4; end • case statements: case (<expression>) <value1>: <statement> <value2>: <statement> default: <statement> endcase

  29. Example: 4-1 MUX in behavioral (1) module mux4 (sel, A, B, C, D, Y); input [1:0] sel; // 2-bit control signal input A, B, C, D; output Y; regY; // target of assignment always @(sel or A or B or C or D) If (sel == 2’b00) Y = A; else if (sel == 2’b01) Y = B; else if (sel == 2’b10) Y = C; else if (sel == 2’b11) Y = D; endmodule A B Y C D Sel[1:0]

  30. Example: 4-1 MUX in behavioral (2) // 4-1 mux using case statement module mux4 (sel, A, B, C, D, Y); input [1:0] sel; // 2-bit control signal input A, B, C, D; output Y; regY; // target of assignment always @(sel or A or B or C or D) case (sel) 2’b00: Y = A; 2’b01: Y = B; 2’b10: Y = C; 2’b11: Y = D; endcase endmodule A B Y C D Sel[1:0]

  31. Example: 4-1 MUX in behavioral (3) // 4-1 mux using case statement module mux4 (select, d, q); input [1:0] select; // 2-bit control signal input [3:0] d; output q; reg q; // target of assignment always @(select or d) case (select) 2’b00: q = d[0]; 2’b01: q = d[1]; 2’b10: q = d[2]; 2’b11: q = d[3]; endcase endmodule

  32. Example: 4-1 MUX in structural module mux4( select, d, q ); input[1:0] select; input[3:0] d; output q; wire q, q1, q2, q3, q4, NOTselect0, NOTselect1; wire[1:0] select; wire[3:0] d; not n1( NOTselect0, select[0] ); not n2( NOTselect1, select[1] ); and a1( q1, NOTselect0, NOTselect1, d[0] ); and a2( q2, select[0], NOTselect1, d[1] ); and a3( q3, NOTselect0, select[1], d[2] ); and a4( q4, select[0], select[1], d[3] ); or o1( q, q1, q2, q3, q4 ); endmodule

  33. Another Example: 4-bit Full Adder using 1-bit Full Adder module FourBitAdder( sum, c_out, x, y, c_in); output [3:0] sum; output c_out; input [3:0] x, y; input c_in; wire c1, c2, c3; fulladder fa0( sum[0], c1, x[0], y[0], c_in ); fulladder fa1( sum[1], c2, x[1], y[1], c1 ); fulladder fa2( sum[2], c3, x[2], y[2], c2 ); fulladder fa3( sum[3], c_out, x[3], y[3], c3 ); endmodule module fulladder( sum, c_out, x, y, c_in ); output sum, c_out; input x, y, c_in; wire a, b, c; xor( a, x, y); xor( sum, a, c_in ); and( b, x, y ); and( c, a, c_in ); or( c_out, c, b ); endmodule

  34. Repetition • // for loop for(i = 0; i < 10; i = i + 1) begin $display(“i = %d", i); end • //while loop i = 0; while(i < 10) begin $display(“i = %d", i); i = i + 1; end • // repeat loop repeat (5) //repeats the block 5 times, begin $display(“i = %d", i); i = i + 1; end

  35. Blocking and Non-blocking Procedural Assignments • The blocking assignment statement (= operator) acts much like in traditional programming languages. Blocking statement must complete execute before the next statement in the behavior can execute. • The non-blocking (<= operator) evaluates all the right-hand sides for the current time unit and assigns the left-hand sides at the end of the time unit. Non-blocking assignment statements execute concurrently rather than sequentially.

  36. References • Cadence Design Systems, Inc., Verilog-XL Reference Manual. • Ciletti, Michael D., Starting Guides to Verilog 2001, Prentice Hall 2004 • http://www.eg.bucknell.edu/~cs320/Fall2003/verilog.html • http://www.verilog.net/index.html • http://www.eecs.berkeley.edu/~culler • http://www-inst.eecs.berkeley.edu/~cs150

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