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Diamond Inner Region for Thermal Modeling

This document outlines the thermal modeling of the diamond inner region within silicon chips, detailing power dissipation metrics for irradiated and annealed silicon. It discusses assumed material properties, including power dissipation rates at 1e16 neq/cm² (~122 mW/cm²) and how these values are adjusted for annealed silicon. The distribution of digital power within the chip is classified into constant pixel power (CPP), constant digital power (CDP), and representative digital power (RDP), culminating in a total power consumption analysis. It notes the temperature changes in low and high power modes, indicating a temperature increase of ~1°C for low power and ~6°C for high power.

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Diamond Inner Region for Thermal Modeling

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  1. Diamond Inner Region for Thermal Modeling Brian Maynard April 30, 2010

  2. Assumed Material Properties

  3. Power dissipationfor irradiated silicon(input to ANSYS) • Power dissipation at 1e16 neq/cm2 ~122 mW/cm2 (from T. Affolder ) For annealed silicon, we simply multiply the above function by 0.57 for an operating voltage of 900V (T. Affolder) It is assumed the silicon is annealed

  4. Power Distribution in Chip Constant Pixel Power (CPP) +1/R Digital Power section of chip (RDP) Constant Digital Power (CDP) (1/14th the area of the total chip) The orange part of the chip (CDP) is situated such that it is farthest away from the beam center CPP + (7.5 mm*RDP)R-1 + CDP = Total Watts/Chip

  5. RDP=CPP=CDP=0.5W/chip Half that was used on next slide

  6. RDP=CPP=CDP=0.5W/chip

  7. Sensor Layer Silicon Diamond

  8. RDP=CPP=CDP=0.5W/chip with Diamond Inner Region

  9. RDP=CPP=CDP=1.5W/chip

  10. RDP=CPP=CDP=1.5W/chip Diamond Inner Region

  11. Summary From a low power mode, the change in temperature is not that significant (~1C) For high power modes the change is more dramatic (~6C)

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