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Introduction to Digital Integrated Circuits: Week One Overview

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This week, we explore the fundamentals of digital systems and integrated circuits. We define digital systems, focusing on key concepts such as Analog to Digital Conversion (ADC), sampling rates, resolution, and digital circuit configurations. The course includes seminars and laboratories every two weeks, featuring topics like state transition and output functions. Students will learn about combinational circuits, timing, and Verilog HDL implementations. Assessment is based on seminar participation, homework, and a final exam.

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Introduction to Digital Integrated Circuits: Week One Overview

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  1. Digital Integrated Circuits- week one - Gheorghe M. Ştefan http://arh.pub.ro/gstefan/ - 2014 -

  2. Course: 3 hours/week • Text book: http://arh.pub.ro/gstefan/0-BOOK.pdf • Seminar: 2 hours every two weeks • Laboratory: 2 hours every two weeks • Grading: • 30% seminar • 40% home works • 30% final exam • Mandatory: 50% from lab & seminar Digital Integrated Circuits - week one

  3. WHAT’S A DIGITAL SYSTEM? • Framing the digital domain • Defining a digital system • Our first target Digital Integrated Circuits - week one

  4. Analog to Digital Conversion (ADC) • s(t): a continuous, analog signal • clock: periodic square wave with frequency fclock = 1/T • sample rate: samples per second (SPS), is given by 1/T • resolution: number of bits used to express the level (3 bits in our example) Digital Integrated Circuits - week one

  5. 1 0 • Both, sample rate and resolution are doubled • Commercial ADC: • up to 6 GSPS • 6 – 24 bits resolution (at 6 GSPS only 12 bits) Digital Integrated Circuits - week one

  6. Generic digital system Digital Integrated Circuits - week one

  7. What is computer science? Digital Integrated Circuits - week one

  8. Digital system. Formal definition DS = (X, Y, S, f, g) X {0,1}nis the n-bit input set Y {0,1}m is the m-bit output set S {0,1}qis the q-bit internal state (state) set f:(X × S) → S is the state transition function g:(X × S) → Y is the output transition function If xt  X, yt  Y, st  S st = f(xt-1, st-1) is a sequential function yt = g(xt, st) is a combinational function Digital Integrated Circuits - week one

  9. Digital Circuit: the simplest embodiment of a Digital System • Binary configurations: • input: Xn-1, Xn-2, … X0 • output: Ym-1, Ym-2, … Y0 • state: Sq-1, Sq-2, … S0 with: Xi, Yj, Sk,  {0,1} coded with: • 0 Volt for 0 • 1-2 Volt for 1 • combinational circuits • registers • clock signal Digital Integrated Circuits - week one

  10. Combinational circuit On inalln-bit binary configurations must be considered Output can change at any input bit switch : always @(*) On out some (rarely all) of m-bit binary configurations are considered tp: propagation time shaded time interval: transition time from F(in1) to F(in2) Digital Integrated Circuits - week one

  11. The Register tsu: set-up time thold: hold time tp: propagation time from active edge of clock to output Tclock: the period of the clock signal … ti-1 ti ti+1 … : discrete ticking time shaded interval: the input can change in this time interval Digital Integrated Circuits - week one

  12. Digital system in Verilog HDL Digital Integrated Circuits - week one

  13. The content of file 0_parameter.v : Color code: blue – reserved words green – comments orange - numbers Digital Integrated Circuits - week one

  14. The result of synthesis stateTransition combinational module is instantiated as stateTrans outputTransition combinational module is instantiated as outTrans fd is the register; its output goes forward to outTrans and backward to close the loop though stateTrans module Digital Integrated Circuits - week one

  15. Our first target Rare and isolated wrong pixels must be corrected. No video sensor is perfect. s(t): the input sample at the moment t s’(t): the corrected sample at the moment t The algorithm: s’(t) = if (s(t)= 0) then (s(t-1) + s(t+1))/2 else s(t) Digital Integrated Circuits - week one

  16. The error Digital Integrated Circuits - week one

  17. The actual timing Digital Integrated Circuits - week one

  18. To make the correction, three successive values: in (t-3] in (t-2) in(t-1) must be loaded as the internal state of the circuit. The structure of the internal state consists of 3 sub-states: State[11:0] = {ss3[3:0],ss2[3:0],ss1[3:0]} State transition function: state(t) = {ss3, ss2, ss1} state(t+1) = {ss2, ss1, in(t)} Output transition function: Out(t) = (ss2 = 0) ? (ss3+ss1)/2 : ss2 Results a latency of 2 clock cycles Digital Integrated Circuits - week one

  19. in = xxxx clock state[11:8] = xxxx state[7:4] = xxxx state[3:0] = xxxx + /2 = 0 ? xxxx x 1 0 sel out = xxxx Digital Integrated Circuits - week one

  20. in = 0111 clock state[11:8] = xxxx state[7:4] = xxxx state[3:0] = xxxx + /2 = 0 ? xxxx x 1 0 sel out = xxxx Digital Integrated Circuits - week one

  21. in = 1001 clock state[11:8] = xxxx state[7:4] = xxxx state[3:0] = 0111 + /2 = 0 ? xxxx 0 1 0 sel out = xxxx Digital Integrated Circuits - week one

  22. in = 1010 clock state[11:8] = xxxx state[7:4] = 0111 state[3:0] = 1001 + /2 = 0 ? xxxx 0 1 0 sel out = 0111 Digital Integrated Circuits - week one

  23. in = 1011 clock state[11:8] = 0111 state[7:4] = 1001 state[3:0] = 1010 + /2 = 0 ? 1000 0 1 0 sel out = 1001 Digital Integrated Circuits - week one

  24. in = 1100 clock state[11:8] = 1001 state[7:4] = 1010 state[3:0] = 1011 + /2 = 0 ? 1010 0 1 0 sel out = 1010 Digital Integrated Circuits - week one

  25. in = 1011 clock state[11:8] = 1010 state[7:4] = 1011 state[3:0] = 1100 + /2 = 0 ? 1011 0 1 0 sel out = 1011 Digital Integrated Circuits - week one

  26. in = 1010 clock state[11:8] = 1011 state[7:4] = 1100 state[3:0] = 1011 + /2 = 0 ? 1011 0 1 0 sel out = 1100 Digital Integrated Circuits - week one

  27. in = 1000 clock state[11:8] = 1100 state[7:4] = 1011 state[3:0] = 1010 + /2 = 0 ? 1011 0 1 0 sel out = 1011 Digital Integrated Circuits - week one

  28. in = 0101 clock state[11:8] = 1011 state[7:4] = 1010 state[3:0] = 1000 + /2 = 0 ? 1001 0 1 0 sel out = 1010 Digital Integrated Circuits - week one

  29. in = 0011 clock state[11:8] = 1010 state[7:4] = 1000 state[3:0] = 0101 + /2 = 0 ? 0111 0 1 0 sel out = 1000 Digital Integrated Circuits - week one

  30. in = 0010 clock state[11:8] = 1000 state[7:4] = 0101 state[3:0] = 0011 + /2 = 0 ? 0101 0 1 0 sel out = 0101 Digital Integrated Circuits - week one

  31. in = 0010 clock state[11:8] = 0101 state[7:4] = 0011 state[3:0] = 0010 + /2 = 0 ? 0011 0 1 0 sel out = 0011 Digital Integrated Circuits - week one

  32. in = 0000 clock state[11:8] = 0011 state[7:4] = 0010 state[3:0] = 0010 + /2 = 0 ? 0010 0 1 0 sel out = 0010 Digital Integrated Circuits - week one

  33. in = 0101 clock state[11:8] = 0010 state[7:4] = 0010 state[3:0] = 0000 + /2 = 0 ? 0001 0 1 0 sel out = 0010 Digital Integrated Circuits - week one

  34. in = 0111 clock state[11:8] = 0010 state[7:4] = 0000 state[3:0] = 0101 + /2 = 0 ? 0011 1 1 0 sel out = 0011 Digital Integrated Circuits - week one

  35. in = 1001 clock state[11:8] = 0000 state[7:4] = 0101 state[3:0] = 0111 + /2 = 0 ? 0011 0 1 0 sel out = 0101 Digital Integrated Circuits - week one

  36. Digital Integrated Circuits - week one

  37. Digital Integrated Circuits - week one

  38. Simulation Digital Integrated Circuits - week one

  39. Simulation (cont) Digital Integrated Circuits - week one

  40. Synthesis: top level Digital Integrated Circuits - week one

  41. Synthesis: second level Digital Integrated Circuits - week one

  42. Synthesis: third level Digital Integrated Circuits - week one

  43. The functions involved in digital pixel correction • The predicate function - (ss2 = 0) - used to detect the wrong pixel • The addition function , used to compute the interpolation • The division by 2 function, used to compute the interpolation • The selection function, according to the result of the predicate function select the result of interpolation or the current value • The storage function, triggered by the active edge of clock, used to store the internal state of the system Digital Integrated Circuits - week one

  44. The first crossing through the matter Main targets: • Form behavioral to structural description in Verilog • Working with simple combinational functions • Learning about the internal structure of register • Simple applications • Provide the motivation for: • Understand the transistor level description of a logic circuit • Designing digital systems using digital circuits Digital Integrated Circuits - week one

  45. DIGITAL CIRCUITS • Combinational circuits • Zero circuit • Selection circuit (multiplexor) • Adder • Divider • Sequential circuits • Elementary latches • Clocked latches (transparent on the active level) • Master-Slave flip-flops (triggered by the active edge) • Register • Applications • Shift register • Counter Digital Integrated Circuits - week one

  46. Combinational circuits Digital Integrated Circuits - week one

  47. Zero circuit: a n-input NOR fan-in: number of inputs of a logic circuit depth: number of logic levels of a logic circuit size: the total number of inputs in all the circuits fan-in = 2 depth = 1 size = 2 fan-in = n depth = 1 size = n fan-in = 8 depth = 7 size = 14 fan-in = 8 depth = 3 size = 14 Digital Integrated Circuits - week one

  48. Selection circuit (multiplexer) out = sel in1 + sel’ in0 Digital Integrated Circuits - week one

  49. Behavioral: Structural: Digital Integrated Circuits - week one

  50. Synthesis result for n = 4 Digital Integrated Circuits - week one

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