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CS 140L Lecture 4

CS 140L Lecture 4. Professor CK Cheng 10/22/02. F-F Shift register Counter (Asynchronous) Counter (Synchronous). Flip flop. D. FDCE. Asynchronous Clear. Q. Inputs Output. CE. C. CLR CE D C Q 1 X X X 0 0 0 X X No change

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CS 140L Lecture 4

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  1. CS 140L Lecture 4 Professor CK Cheng 10/22/02

  2. F-F • Shift register • Counter (Asynchronous) • Counter (Synchronous)

  3. Flip flop D FDCE Asynchronous Clear Q Inputs Output CE C CLR CE D C Q 1 X X X 0 0 0 X X No change 0 1 1 1 0 1 0 0 CLR Clock Enable CLK = 1 CLK = 0

  4. Q D CLK CLK tsetup thold t D t Q t tcq

  5. 2) 3 bit shift register B D C A Q Q Q D D D CLK Time Steps A B C D • 0 0 X X X • 1 0 X X • 2 0 1 0 X • 1 0 1 0 • 1 1 0 1 • 0 1 1 0 • 0 0 1 1 • 1 0 0 0

  6. 3 bit counter (asynchronous) A B C Q Q Q 1 1 T T 1 T CLK Assume A(0) = B(0) = C(0) = 0 Time C B A • 0 0 0 0 0 • 1 1 1 7 • 2 1 1 0 6 • 1 0 1 5 • 1 0 0 4 • 0 1 1 3 • 0 1 0 2 • 0 0 1 1 CLK t A 1 0 1 0 t B 1 1 0 0 t C 1 1 1 1 t 7 6 5 4

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