html5-img
1 / 9

Special Pins

Special Pins. A Very Basic Topic But A Source of Frequent Failures and Problems. Termination of Special Pins. MODE pin (test program mode). V PP pin (programming voltage). TRST* (Reset to JTAG TAP controller) TCLK (provides clock to TAP controller) SDI, DCLK (varies for each device type)

azriel
Télécharger la présentation

Special Pins

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Special Pins A Very Basic Topic But A Source of Frequent Failures and Problems

  2. Termination of Special Pins • MODE pin (test program mode). • VPP pin (programming voltage). • TRST* (Reset to JTAG TAP controller) • TCLK (provides clock to TAP controller) • SDI, DCLK (varies for each device type) • Others

  3. MODE Pin • Left Floating • Device can be non-functional • High currents • Uncontrolled I/O • Tied High During Test • Working device stopped functioning • Power supply rise time key

  4. MODE Register Y1 Register Y2 Register X2 Register X1 Register Other Registers MODE Pin - Test, Debug and Programming Control

  5. MODE Pin - Test, Debug and Programming Control

  6. CLK TCLK OSC IEEE JTAG 1149.1 TCLK The CLK pin may turn into an output driving low, clamping the oscillator’s output at a logic ‘0’. The TAP controller can not reset and restore I/O operation. Most FPGAs do not have the optional TRST* pin. Note TRST*, when present, has a pull-up.

  7. IEEE JTAG 1149.1 TCLK Shift Register is undefined in TEST-LOGIC-RESET State TAP Controller (State Machine) TCK Shift CLK TDI Shift Register TDO Reset Chip Control Parallel Latch Latch

  8. SYSTEM BIDIRECTIONAL OUTPUT IEEE JTAG 1149.1 - Scan Path SERIAL INPUT SERIAL INPUT SYSTEM SCAN 2 - STATE CELL OUTPUT SCAN SYSTEM CELL LOGIC SCAN SYSTEM EN CELL INPUT 3 - STATE SCAN OUTPUT CELL ON-CHIP LOGIC SCAN CELL EN SCAN SCAN CELL CELL

  9. IEEE JTAG 1149.1 - Scan I/O Cell To Next Pin Out Enable System Logic Data Out Data In JTAG DATA PATH

More Related