Estimating Power Activity Factors and Understanding Nonideal Transistor Theories

1. Lecture 7: Power

2. Activity Factor Estimation • Activity factor: probability athat a node switches 0→1 • Define probability Pi that a node is “1” • Probability that a node is “0” is then Pi = 1-Pi • ai = Pi * Pi • Completely random data has P = 0.5 and a = 0.25 • Data is often not completely random • Data propagating through ANDs and ORs has lower activity factor • Depends on design, but typically a≈ 0.1 7: Power

3. Switching Probability 7: Power

4. Example • A 4-input AND is built out of two levels of gates • Estimate the activity factor at each node if the inputs have P = 0.5 NAND: If A and B are ”ones” there will be a ”0” output: PNAND=1-PAPB NOR: If n1 and n2 are ”zeroes” there will be a ”1” output: PNOR=P1P2 NAND NOR NAND 7: Power

5. ON and OFF Current • Ion = Ids @ Vgs = Vds = VDD • Saturation • Ioff = Ids @ Vgs = 0, Vds = VDD • Cutoff 4: Nonideal Transistor Theory

6. Leakage Sources • Subthreshold conduction • Transistors can’t abruptly turn ON or OFF • Dominant source in contemporary transistors • Gate leakage • Tunneling through ultrathin gate dielectric • Junction leakage • Reverse-biased PN junction diode current 4: Nonideal Transistor Theory

7. Leakage • What about current in cutoff? • Simulated results • What differs? • Current doesn’t go to 0 in cutoff 4: Nonideal Transistor Theory

8. DIBL • Electric field from drain affects channel • More pronounced in small transistors where the drain is closer to the channel • Drain-Induced Barrier Lowering • Drain voltage also affect Vt • High drain voltage causes current to increase. 4: Nonideal Transistor Theory

9. Threshold Voltage Effects • Vt is Vgs for which the channel starts to invert • Ideal models assumed Vt is constant • Really depends (weakly) on almost everything else: • Body voltage: Body Effect • Drain voltage: Drain-Induced Barrier Lowering • Channel length: Short Channel Effect 4: Nonideal Transistor Theory

10. Body Effect • Body is a fourth transistor terminal • Vsb affects the charge required to invert the channel • Increasing Vs or decreasing Vb increases Vt • fs = surface potential at threshold • Depends on doping level NA • And intrinsic carrier concentration ni • g = body effect coefficient 4: Nonideal Transistor Theory

11. Body Effect • Body is a fourth transistor terminal • Vsb affects the charge required to invert the channel • Increasing Vs or decreasing Vb increases Vt • fs = surface potential at threshold • Depends on doping level NA • And intrinsic carrier concentration ni • g = body effect coefficient 4: Nonideal Transistor Theory

12. Body Effect Cont. • For small source-to-body voltage, treat as linear 4: Nonideal Transistor Theory

13. Gate Leakage • Carriers tunnel thorough very thin gate oxides • Exponentially sensitive to tox and VDD • A and B are tech constants • Greater for electrons • So nMOS gates leak more • Negligible for older processes (tox > 20 Å) • Critically important at 65 nm and below (tox≈ 10.5 Å) From [Song01] 4: Nonideal Transistor Theory

14. Subthreshold Leakage • Subthreshold leakage exponential with Vgs • n is process dependent • typically 1.3-1.7 • Rewrite relative to Ioff on log scale • S ≈ 100 mV/decade @ room temperature 4: Nonideal Transistor Theory

15. Subthreshold Leakage • For Vds > 50 mV • Ioff = leakage at Vgs = 0, Vds = VDD Typical values in 65 nm Ioff = 100 nA/mm @ Vt = 0.3 V Ioff = 10 nA/mm @ Vt = 0.4 V Ioff = 1 nA/mm @ Vt = 0.5 V h = 0.1 kg= 0.1 S = 100 mV/decade 7: Power

16. Stack Effect • Series OFF transistors have less leakage • Vx > 0, so N2 has negative Vgs • Leakage through 2-stack reduces ~10x • Leakage through 3-stack reduces further 7: Power

17. NAND3 Leakage Example • 100 nm process Ign = 6.3 nA Igp = 0 Ioffn = 5.63 nA Ioffp = 9.3 nA Data from [Lee03] 7: Power

18. Lecture 10: Circuit Families

19. Outline • Pseudo-nMOS Logic • Dynamic Logic • Pass Transistor Logic 10: Circuit Families

20. Introduction • What makes a circuit fast? • I = C dV/dt -> tpd (C/I) DV • low capacitance • high current • small swing • Logical effort is proportional to C/I • pMOS are the enemy! • High capacitance for a given current • Can we take the pMOS capacitance off the input? • Various circuit families try to do this… 10: Circuit Families

21. Pseudo-nMOS • In the old days, nMOS processes had no pMOS • Instead, use pull-up transistor that is always ON • In CMOS, use a pMOS that is always ON • Ratio issue • Make pMOS about ¼ effective strength of pulldown network 10: Circuit Families

22. Dynamic Logic • Dynamic gates uses a clocked pMOS pullup • Two modes: precharge and evaluate 10: Circuit Families

23. The Foot • What if pulldown network is ON during precharge? • Use series evaluation transistor to prevent fight. 10: Circuit Families

24. Monotonicity • Dynamic gates require monotonically rising inputs during evaluation • 0 -> 0 • 0 -> 1 • 1 -> 1 • But not 1 -> 0 10: Circuit Families

25. Monotonicity Woes • But dynamic gates produce monotonically falling outputs during evaluation • Illegal for one dynamic gate to drive another! 10: Circuit Families

26. Domino Gates • Follow dynamic stage with inverting static gate • Dynamic / static pair is called domino gate • Produces monotonic outputs 10: Circuit Families

27. Charge Sharing • Dynamic gates suffer from charge sharing 10: Circuit Families