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Evaluation of Mentor-IS Tool for Designing Fast Ethernet Switch and Problematic Board

This project aims to evaluate the Mentor-IS tool by designing a fast, problematic board using Orcad Capture. It features two versions of a fast Ethernet switch with 8 ports, utilizing both Galileo’s and Technion’s design tools. The current project status shows completion of design, installation, and evaluation of the board. Key evaluations include data flow analysis, simulation validity, synthesis power, and comparison with real boards. The report includes impressions of the IS interface, stability, customer support, and student insights.

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Evaluation of Mentor-IS Tool for Designing Fast Ethernet Switch and Problematic Board

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  1. GT 48310A Evaluation board &Inter Connectics (IS) evaluation Student: ZIV HAREL Instructors: Moni & Inna (digital lab) Ilan levin (Galileo)

  2. Description : • The first goal is to evaluate the Mentor-IS tool - by using it to design a fast , problematic board , which was logically designed in Orcad Capture. • The second goal is to design & check an Expandable 8 ports fast Ethernet switch. • 2 board versions : 1. Galileo’s (“very best” tool) 2. Technion’s (Mentor tool)

  3. The board (IS view)

  4. Project status • Board : design : done. Installation : done. Checking : done. • IS evaluation : board design : done. Simulation : done.Synthesize : done. (for critical lines) Pre-production : done. Final simulation: now.

  5. Contents : • What was evaluated . • The data-flow . • Notes . • Where did I use it ? • Comparison to real board. • My impression about IS .

  6. What was evaluated • IS installation -> stabilization. • Design manager installation->stabilization .PC/Unix versions. • Work flow. • IBIS models. • The IS tool : - Simulation Validity / synthesis power . - IS Interface . • Mentor’s Support .

  7. ORCAD to MENTOR’S IS data-flow designer editor Designer(?) 1 2 3 4 5 6 packages, geometry. Placement , routing Translate files to IS data-base , simulate & synthesize . Translate the components file to Mentor format. Create the Design in Orcad Capture Validate the packaging and geometry data. Mentor board station IS Orcad

  8. Notes • Orcad ->edif ->Design-arch : failed . • Orcad ->comp & Netlist -> Mentor :format mismatch : solved . • Back annotation to Orcad : failed. • Stable -work -flow : solved. • Designer / c.editor / IS relationship: not sorted yet...

  9. More - notes : • IBIS Models :- non-monotonic models : work around … - availability,accuracy : partly solved. - models for capacitors : work around … - models for Magnetics : failed. • Synthesis: - defining the real load : work around … - handling skew capacitors : work around …

  10. Where did I use it ? • Fast signals: - 125Mhz clk to 2xSdram & GT48310A. Needed 0.05ns max skew , low noise. - 83.33Mhz clk to 2xSdram & Glink & GT48310A (same as 125M_clk ). - Sdram signals - addr/data - 0.5ns delay. • Differential lines: (couldn't use the IS) Needed 0.5ns max skew , low noise. - differential Tx/Rx lines :same length , needed low : noise - 50mv max.

  11. Comparison to real board • The comparison can’t be accurate - the boards are not identical ! • IS predicted correctly signal shape and levels . • IS was too pessimist - circuit is robust!

  12. Fast clock circuits : Clk distributor 125Mhz oscillator GT48310A 2 x SDRAM not all resistors are drown . Main Clk distributor Alternative supply . 83.3Mhz source GT48310A 2 x SDRAM GT48300

  13. 125Mhz clk - after routing

  14. 125Mhz clk - on board

  15. Core clk after routing

  16. Core clk - on board

  17. My impression about IS • Work flow . • User interface . • Stability . • Synthesis power/simulation validity . • Was it right ??? • Other tools interfacing IS. • Customer support . • Notes from companies tour .

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