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MOTOROLA 68HC08 INTRODUCTION AND SYSTEM OVERVIEW

MOTOROLA 68HC08 INTRODUCTION AND SYSTEM OVERVIEW. CONTENTS. 68HC08 Micro Controller Family Evolution CSIC Design Philosophy CPU08 Overview 68HC708 Architecture Overview Module Preview 68HC08 Technical Support. MPC600. Most Powerful. 32- &. MPC500. RISC. 68020. 68300. 15 Versions.

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MOTOROLA 68HC08 INTRODUCTION AND SYSTEM OVERVIEW

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  1. MOTOROLA68HC08INTRODUCTIONANDSYSTEM OVERVIEW

  2. CONTENTS • 68HC08 Micro Controller Family Evolution • CSIC Design Philosophy • CPU08 Overview • 68HC708 Architecture Overview • Module Preview • 68HC08 Technical Support

  3. MPC600 Most Powerful 32- & MPC500 RISC 68020 68300 15 Versions 68000 68HC16 16-Bit 68HC12 12 Versions 2 versions 68HC11 60 Versions 68HC08 6800 15 Versions 8-Bit 68HC05 180 Versions Least Expensive Motorola's 6800 Family Evolution Hardware Compatibility Architecture Software Compatibility Time

  4. Design Goals for 8-bit Microcontrollers • Broad product offering for tiered performance application needs • Higher performance, cost sensitive • Easy migration path for existing 68HC05 users • Ability to meet new customer requirements quickly • Low voltage capable • High quality, cost effective manufacturing capabilities • Documentation and development support

  5. Motorola's Solution: The 68HC08 CPU • HC05 object code compatible • Architecturally enhanced 68HC05 CPU • 5x average performance increase • CSIC's first unified design rules (UDR) core • New module based CSIC design/test methodology • CPU architecture extensibility

  6. 68HC08 Modular CSIC Solution • Modularity Requirements • Standard internal bus definition • Standard module heights • Standard module definition • Reduced Die Size (Cost-effectiveness) • Individual modules hand packed to take up less silicon • No excessive glue logic

  7. CSIC LIBRARY CPU SIM DMA ADX EXT TIM 68HC08 CPU BUS CPM RTC PLL SCI PWM LCD SPI OSD OSC A/D PTA PTB MEM GEN PTC PTD CPM – CUSTOMER PROPRIETARY MODULE Building a CSIC from a Module Library MC68HC08

  8. 68HCxx 8-BIT CPU Cores Major Differences HC05 Single Chip Operation (except for 68HC05C0) No Direct Control of the Stack Pointer One 8-Bit Index Register One 8-Bit Accumulator 8-Bit Math with MUL Instruction IDR Process (4Mhz bus) HC08 Single Chip and Expanded Modes Direct Control of Stack Pointer via PUSH/PULL Instructions One 16-Bit Index Register One 8-Bit Accumulator 8-Bit Math with MUL and DIV Instructions UDR Process (8 Mhz bus) HC11 Single Chip and Expanded Modes Direct Control of Stack Pointer via PUSH/PULL Instructions Two 16-Bit Index Register Two 8-Bit Accumulator or One 16-Bit Accumulator 16-Bit Math with MUL and DIV instructions IDR P Process (4 Mhz bus)

  9. Let's take a closer look at the CPU IRQ Module LVI Module Clock Generation Module System Integration Module 68HC08 CPU Timer Module Peripheral Module RESET Module COP Module Internal Bus (IBUS) DMA Module Peripheral Module Peripheral Module RAM Memory ROM Type Memory Peripheral Module BREAK Module

  10. 68HC08 CPU Design Accomplishments • Increased Bus Speed of 8Mhz at 5V • Sub-micron UDR process • Improved Instruction Set and Addressing Modes • Opcode Look-Ahead Instruction Prefetch • Optional Modular Extensions • DMA module reduces interrupt overhead • Address extension module increases address bus to 24-bits for > 64K data/program space

  11. 68HC08 Instruction Preview • Data Movement • Load, Store, Move, Stack • Arithmetic • Add, Sub, Mul, Div • Logical • And, Or, Eor • Data and Bit Manipulation • Shifts, Rotates, Bit Test • Program Control • Branch, Subroutine • Binary Coded Decimal • Looping Constructs • Special High Level Language Support

  12. 68HC08 Addressing Preview • Inherent • Immediate • Direct • Extended • Indexed • 8 and 16 bit offset • Stack Pointer • Post Increment • Relative • Memory to Memory • Direct • Indexed

  13. 68HC08 Instruction/Addressing Summary • Stack Manipulation (48 new instructions) • Directly push/pull any register & add immediate to stack • Stack relative addressing mode • Temporary variables on the stack can be manipulated directly, without loading them into the accumulator • Index Extension Register (7 new instructions) • Allows use of full 16-bit index register (H:X) • Memory to Memory Move (4 new instructions) • Looping Constructs (12 new instructions) • Decrement and Branch • Compare and Branch • Arithmetic Enhancements (1 new instruction) • Faster multiply (5 clks vs 11) • Divide (16/8) • BCD Support (2 new instructions) • Decimal adjust accumulator and nibble swap accumulator • C Compiler Support (4 new instructions) • Conditional branch with signed operands

  14. IRQ LVI Direct Memory Access Module Clock System 68HC08 CPU Timer Interface Module Generation Integration RESET Module Module BREAK COP Internal Bus (IBUS) Serial Peripheral Interface Serial Communications Interface Random Access Memory Electronically Programmable ROM Monitor ROM 68HC08 FlagshipMC68HC708XL36 • Architecturally Enhanced 8-bit CPU • 1Kbyte RAM and 36Kbytes EPROM • 240 Bytes Monitor ROM • System Control and Protection Modules (SIM) • Direct Memory Access Module (DMA) • General Purpose Timing Interface Module (TIM) • Serial Communication Modules (SCI and SPI)

  15. CPU SYSTEM MODULES • Low Voltage Inhibit (LVI) • Computer Operating Properly (COP) • Break Module • External Interrupt Module (IRQ) • System Integration Module (SIM) • Manages System Protection • Reset on illegal address and illegal opcode • Optional reset on LVI and COP • Manages Interrupts with up to 128 separate vectors • Bus Clock Generation for CPU and most Peripherals • CLOCK GENERATION MODULE(CGM) • Provides clock inputs into SIM Module and SCI Baud Generator • Crystal Oscillator circuit and phase locked loop circuit • Avoids the cost and noise of high frequency crystals • Programmable bus frequency • Integer multiples (1 to 15) of crystal frequency ÷ 4 • TIMING INTERFACE MODULE (TIM) • Modular architecture • 68HC05C4 timer compatible channels • Input capture, Output Compare, PWM • Counter may be free-running or modulo up-counter • Optionally toggle any channel output on overflow • Timer interrupts can select CPU or DMA servicing

  16. DIRECT MEMORY ACCESS (DMA) • DMA can be used to reduce CPU overhead of processing normal data movement interrupts • Using DMA to service peripherals instead of CPU interrupts can dramatically reduce interrupt overhead • A byte transfer takes only two clocks (4 MByte/sec peak) • CPU processing continues after the DMA transfer as if nothing happened • Allows transfers between any two CPU addressable locations • Expandable architecture up to seven channels • Block transfer capability of up to 256 bytes • Programmable bus bandwidth utilization of 25% to 100% • Optional CPU interrupt upon completion data block transfer • Optional enable for DMA operation during low power wait • SERIAL PERIPHERAL INTERFACE (SPI) • Compatible with HC05 SPI but with enhancements: • Separate receive and transmit buffers avoid write collisions • Programmable wired-or mode • DMA can service normal data movement SPI interrupts

  17. SERIAL COMMUNICATIONS INTERFACE (SCI) • Compatible with HC05 SCI but with enhancements: • Optional HW parity • Two idle line receiver wakeup methods • Additional interrupt vectors and interrupt enables • Loop mode for diagnostics/test • DMA can service normal data movement SCI interrupts • MEMORY MODULES • 1 KByte fully static 8-bit RAM • 36 KBytes of 8-bit user-programmable ROM • Windowed packages available for UV erasure • One-time programmable non-windowed packages • EPROM security mode

  18. New Module Development • Modules currently in design or targeted2, 6, & 8 Channel Programmable Timers • Dedicated 8-bit & 16-bit Pulse Width Modulation • Analog/Digital Converter (8-bit and 10-bit) • External Bus Interface • Address Extension • Comparators • RAM • EPROM • ROM • EEPROM • I2C • LCD • Customer Specific • OSD - On Screen Display

  19. 68HC08 Summary • Architecture is an extension of the world's leading 8-bit microcontroller family - 68HC05 • Offers a high performance, cost-effective migration for existing HC05 applications • Modular design and test methodology gives Motorola ability to meet customer new product requirements with dramatically lower cycle time • Supported by a portfolio of development tools to program, evaluate and design applications

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