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IC-SOC STEAC: An SOC Test Integration Platform

IC-SOC STEAC: An SOC Test Integration Platform

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IC-SOC STEAC: An SOC Test Integration Platform

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  1. IC-SOCSTEAC: An SOC Test Integration Platform Cheng-Wen Wu

  2. Outline • Introduction • Test Access Control System (TACS) • Test Pattern Application • Test Time Calculation • Test Integration Issues and Solutions • Test Scheduling • IO Reduction for Test Control Signals • Timing Issues in Functional Test • Scan and Functional IO Sharing • Experimental Results • Conclusions DTC, NTHU

  3. Introduction • Test scheduling is one of the most important challenges in SOC testing • Test IO utilization • SOC test time reduction • Previous works discuss TAM architectures and core test scheduling, assuming fixed IOs for test control • Without considering realistic test architecture • Too optimistic • We define test scheduling based on Test Access Control System (TACS) [TECS02] • Consider TAM, test control and the IO constraint DTC, NTHU

  4. IEEE P1500-Based Test Architecture • P1500 Test Wrapper provides circuit isolation and test access for embedded cores • Serial access & parallel access K.-L. Cheng, et al.,”An SOC Test Integration Platform and Its Industrial Realization”, ITC’04 DTC, NTHU

  5. Test Access Control System (TACS) • Our scheduling model is based on our TACS architecture • IEEE 1149.1 compliant TAP Controller • Controls operation of P1500 Test Wrapper • Configures TAM • Sends test patterns and receives test response through its TAM IO • Multiplexer-based TAM bus • Only a small number of IOs are needed for test control • 5 inputs for TDI, TMS, TCK, TRST, and TSE • 1 output for TDO DTC, NTHU

  6. TACS Architecture DTC, NTHU

  7. TAM Architecture of TACS • Hybrid TAM architecture • Combine multiplexing architecture and distribution architecture • Session-based test scheduling • Simpler test controller and TAM arbitration circuit • Lower test scheduling complexity DTC, NTHU

  8. HDL Designs with DFT information Verilog Parser STIL Parser Core Test Scheduler TACS Generator TAM Generator Wrapper Generator Test Insertion Wrapper Pat. Trans. System Pat. Trans. Testable HDL Designs STEAC Test Integration Flow DTC, NTHU

  9. The Test Scheduling Problem Given: (1) test information of each core; (2) test resource constraints (including TAM and test control) Determine: (1) order of core tests; (2) test resource allocated to each core Such that: total test time is minimized (by exploring the highest degree of parallelism) • Assumptions in previous works: • Test time is the product of vector number and shift path length • Powerful controller  high area overhead • Multiple sets of control IOs  high test I/O count • Each core can be tested at any time • Powerful controller & complex TAM arbitration DTC, NTHU

  10. Realistic Test Modeling • Test time calculation under TACS PA: number of test vectors for Core A PB: number of test vectors for Core B LA: number of cycles to Load/Unload test data for Core A LB: number of cycles to Load/Unload test data for Core B; LA>LB vector 1: [L, A, U] L: Load A: Apply U: Unload vector 2: [L, A, U] Core A & Core B vector (P -1): [L, A, U] A vector P : [L, A, U] A vector (P +1): [L, A, U] A Core B vector (P +2): [L, A, U] A only vector P : [L, A, U] B PA(LA+5)+PA (PB-PA)(LB+5) DTC, NTHU

  11. IO Resource Constraint • Test cost is also related to test IO channels • Package and tester • Simpler test controller  fewer test IOs  better TAM utilization  shorter test time  lower test cost • When developing a test methodology for SOC, we should compare the test time under the same test IO resource constraint DTC, NTHU

  12. 3 5 TSC1: core1 and cor4 TSC2: core2 and core5 TSC3: core3 2 4 1 Test IO Reduction • All clock, reset, and test enable signals must be directly controlled • If cores are not tested concurrently, they can share the same clock and reset signals • Need 3 test clock signals and 3 test reset signals • Test enable signals are generated by the test controller DTC, NTHU

  13. Test Time Calculation • Example: Cores A and B are tested concurrently in the same session • Shift length LA > shift length LB • Pattern count PB > pattern count PA • The test time of this session: • PA x (LA +5) +LA + (PB - PA) x LB • Can the test time be further reduced? A B LA PA x (LA +5) (PB - PA) x LB A Original B Further reduced A B DTC, NTHU

  14. Scan and Functional IO Sharing DTC, NTHU

  15. Typical Test Scheduling Method • Sort the cores by test time, assuming 1-bit TAM for each core • Initial schedule: • Order the cores from longest test time to shortest test time • Give a start point to our branch and bound scheduling algorithm • Schedule all the cores with its max Pareto-optimal points • Perform a branch and bound algorithm • Only try the Pareto-optimal points of each core • Finally, get the best result from our algorithm DTC, NTHU

  16. Experimental Result • The test time improvement is ΔTmax(%) = 100 x (original Tmax – improved Tmax ) / original Tmax • Example: core A and core B are tested in the same session • LA = 218 , LB = 48 • PA = 45, PB = 160 • Original test scheduling • Test time = 45 x (218+5)+218+ (160 – 45) x 48 = 15,773 • Improved test scheduling • Test time = max{45x(218+5)+218,160x(48+5)+48}=10,253 • Test time improvement = 35.0% DTC, NTHU

  17. Conclusions • We propose a practical SOC test scheduling scheme under test IO constraint • Our TACS architecture only needs fixed number of test controls • We propose a new method which allows test IO sharing in different test sessions • Reducing the test IO number • We also propose a method to shifting test patterns independently for different cores in a test session • Further reducing the test session time DTC, NTHU