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Focus on Physics Case for Pixel Upgrade TDR Upgrade Pixel Software and CMSSW Integration

Physics and Computing Issues Harry Cheung ( Fermilab ) Presenting work of the Tracker Upgrade Simulations Group. Focus on Physics Case for Pixel Upgrade TDR Upgrade Pixel Software and CMSSW Integration Pixel Upgrade Simulation Tracking Performance

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Focus on Physics Case for Pixel Upgrade TDR Upgrade Pixel Software and CMSSW Integration

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  1. Physics and Computing IssuesHarry Cheung(Fermilab)Presenting work of the Tracker Upgrade Simulations Group Focus on Physics Case for Pixel Upgrade TDR Upgrade Pixel Software and CMSSW Integration Pixel Upgrade Simulation Tracking Performance Software and Computing Issues for Physics Case CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  2. Introduction: Focus on TDR • Demonstrate and strengthen physics case for upgrade TDR • Update simulation studies and results for tracking performance • CMSSW software version update, tracking, details in parallel session • SridharaDasu will present on other subsystems • Study pixel Phase 1B scenario (with modified inner layer) • Smaller pixel size, thinner sensor (lower threshold), smaller radius • Demonstrate gain for upgrade in at least one physics channel • Use CMSSW, update on data samples & software/computing issues CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  3. Pixel Phase 1 Geometry • Phase 1 pixel detector replacement • 4 barrel layers, outermost layer closer to TIB • 3 FPIX disks per side, split into inner and outer disks • New ROC chip, readout, power, cooling, etc.: Total material less than in current pixel detector Phase 1 BPIX geometry Current BPIX geometry CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  4. Pixel Upgrade Material Budget • Reduced material even with more layers Rad. Len. Nucl. Int. Len. Pixels Pixels Dots – Curr geom Green – Upgrade CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  5. Upgrade Software • Upgrade simulation software is part of CMSSW • Mostly integrated (incl. bug fixes, speedups). Have CMSSW release CMSSW_4_2_3_SLHCx (Stick with this for TDR studies) • Some code in branches still to be merged in CMSSW main trunk • Implement fake conditions and data loss scenarios (e.g. via upgrade DB entries and global tags) • Rid of hardcoded parameters e.g. pixel size, threshold, ADC bits, tracker geometry (e.g. via merged code with configurable parameters) • Tracking software changes to account for extra pixel layers (e.g. seeding) (via merged code with configurable parameters) • Change parts of Fastsim geometry that are hardcoded (need FW solution) • Tracking studies for TDR • Use CMSSW_4_2_3_SLHCx with CMSSW_4_4_X tracking • Iterative tracking changes for CPU and memory reduction CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  6. Upgrade Tracking • Study at 2×1034 cm-2s-1,<PU>=50 (100) for 25 (50) ns • Data loss used in simul. due to ROC/readout limitations (from TP) • Tracking steps modified for upgrade geometry and high PU • Extra layer: quadruplet seeds and efficient triplet seeding (3-out-of-4) • Tuning of tracking steps for <PU> of 50 and 100 to reduce fakes • Drop pair seeds, low pT seeds, and detached tracking steps • Optimization still ongoing CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  7. Tracking Efficiency & Fake rate • Using MultiTrackValidator, Muon flat pT, high purity tracks Fake Rate Efficiency eta Fake Rate Efficiency pT No Pileup <PU>=50 no data loss <PU>=50 with (Pixel ROC) data loss Effect of ROC data loss: Loss of tracking efficiency, fake rate the same CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  8. Tracking Efficiency & Fake rate • Using MultiTrackValidator, ttbar sample, high purity tracks Fake Rate Efficiency eta Fake Rate Efficiency pT No Pileup <PU>=50 no data loss <PU>=50 with (Pixel ROC) data loss Effect of ROC data loss: Loss of tracking efficiency, fake rate the same CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  9. Tracking Efficiency & Fake rate • Using MultiTrackValidator, ttbar sample, high purity tracks No Pileup Fake Rate Efficiency eta Fake Rate Efficiency pT Upgrade improves tracking efficiency, and fake rates at high PU Current Pixel Geometry Phase 1 Upgrade Geometry CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  10. Transverse IP Resolutions vs p • Compare Std Geometry and Phase 1 zero PU using muons Current Pixel Geometry Phase 1 Upgrade Geometry 0 < η < 1.0 1.0 < η < 1.5 1.5 < η < 2.0 2.0 < η < 2.5 CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  11. Longitudinal IP Resolutions vs p • Compare Std Geometry and Phase 1 zero PU using muons Current Pixel Geometry Phase 1 Upgrade Geometry 0 < η < 1.0 1.0 < η < 1.5 1.5 < η < 2.0 2.0 < η < 2.5 CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  12. Primary Vertex Resolution vs Ntk • Compare Std Geometry and Phase 1 zero PU and <PU>=50 using ttbar No pileup <PU>=50 Transverse Current Pixel Geometry Phase 1 Upgrade Geometry <PU>=50 No pileup Longitudinal CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  13. B-Tagging Performance • Using b-tagging validation, ttbarsample, no pileup No Pileup Track Counting HE Simple Secondary Vertex HE Combined Secondary Vertex CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  14. B-Tagging Performance • <PU>=50, ttbar, no tuning of b-tag algos <PU>=50 Track Counting HE Simple Secondary Vertex HE No tuning done for high pileup: CVS seems to perform the best at high PU Combined Secondary Vertex CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  15. B-Tagging Performance • <PU>=50, ttbar, effect of ROC dataloss • Improvement for upgrade geometry even without ROC data loss CombinedSecondaryVertex b-tagging algorithm <PU>=50 with (Pixel ROC) data loss <PU>=50 no data loss CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  16. B-Tagging Performance • <PU>=50, ttbar, no tuning of b-tag algos Significant improvement in b-jet tagging efficiency at fixed mistag rate, (or in mistag rate for fixed b-jet tagging efficiency Medium CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  17. B-Tagging Performance • Compare <PU>=100 and 50, ttbar, no tuning of b-tag algos Need tuning and optimization of tracking and b-tagging algorithms at <PU>=100 Relevant if we run with 50 ns crossing time at 2×1034 cm-2s-1 CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  18. Simulations for Physics Case • Study the boosted ZH μμbb-bar channel as in the TP • Channel still relevant in the >100 fb-1 regime • Use CMSSW simulation instead of generator analysis used in TP • Use Modified Fastsim: simhits (including PU) from fastsim but then the regular Fullsim digi steps and full track pattern recognition • Faster and lower memory usage, Fullsim digi+reco step needs >4GB RAM/job slot (max 2-3 GB/slot on GRID) ttbar: LPCCAF CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  19. “Validate” Modified Fastsim 4 Physics • Compare modified FastsimvsFullsim, ttbar, No Pileup • Modified Fastsim: use Fastsim for simhits & pileup only Fullsim Modified Fastsim Phase 1 geometry Current Geometry CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  20. Tracking Efficiency & Fake rate • Compare Fastsim, ttbar, <PU>=50 • Modified Fastsim: use Fastsim for simhits & pileup only Fullsim Modified Fastsim Phase 1 geometry Current Geometry CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  21. Tracking Efficiency & Fake rate • Compare Fastsim, Muon gun (flat pT), No Pileup • Modified Fastsim: use Fastsim for simhits & pileup only Fullsim Modified Fastsim Phase 1 geometry Current Geometry CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  22. Tracking Efficiency & Fake rate • Compare Fastsim, Muon gun (flat pT), <PU>=50 • Modified Fastsim: use Fastsim for simhits & pileup only Fullsim Modified Fastsim Phase 1 geometry Current Geometry CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  23. B-Tagging Performance • Compare Fastsim, ttbar, No Pileup • Modified Fastsim b-tagging performance similar for a wide operating CombinedSecondaryVertex b-tagging algorithm Phase 1 geometry Current Geometry CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  24. B-Tagging Performance • Compare Fastsim, ttbar, <PU>=50 • Modified Fastsim b-tagging performance similar for a wide operating range of b-jet b-tagging efficiencies (despite fake rate difference) CombinedSecondaryVertex b-tagging algorithm Phase 1 geometry Current Geometry CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  25. B-Tagging Performance • Compare Fastsim, ttbar, <PU>=50 • Modified Fastsim b-tagging performance looks similar enough at <PU>=50 to do comparative physics studies CombinedSecondaryVertex b-tagging algorithm Fullsim Modified Fastsim CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  26. B-Tagging Performance • However! Compare Fastsim, ttbar, <PU>=100 • Modified Fastsim b-tagging performance very different from Fullsim! CombinedSecondaryVertex b-tagging algorithm Current Geometry CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  27. MC Samples Requested • 10K Fullsim signal & background samples produced • Samples look okay to proceed with large samples • 10K modified Fastsim samples being validated • Fullsim GEN-SIM samples requested, being processed • Need to request digi+reco with AOD output after this • Take ~1-2 weeks on 1000 job-slot farm (not unreasonable timescale) • Started working with CMS VHbbAnalysisNewCode • Learning stage (more complex than generator analysis) CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  28. Summary • We have updated the fullsim MC results for tracking and b-tagging performance for the TDR. Shows that the Phase 1 upgrade pixel detector can provide significant improvements at 2×1034 cm-2s-1 • Can still improve tuning of track reconstruction, and investigating high pileup performance of the b-tagging algorithms (to improve it – it’s a core CMS task) • We need (new) results for the Phase 1B scenario • A modified Fastsim can significantly reduce CPU time and memory usage, and can be used for generating samples for a physics study • The tracking efficiency and b-tagging performance of the modified fastsim compares well with the Fullsim, for ttbar, but some differences in muon efficiencies at <PU>=50 and significant differences for b-tagging at <PU>=100 • In the process of generating fullsim and fastsim AOD samples relevant to the associated Z(μμ)H(bb-bar) analysis • Working with the “official CMS” VHbb analysis code (learning stage) • Will need to produce larger background samples (use Fastsim if validated) • Could use more help for this • We have a 4_2_X version of the Phase 2 simulation also • In use by Track Trigger Task Force, see talks in Tuesday meeting CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  29. Backup Slides CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  30. Standard Tracking Steps • 4_4_0_pre6 tracking steps: includes pair seeds, lower pT seeds, and detached tracks CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  31. Tracking Efficiency & Fake rate • Using MultiTrackValidator Tracking efficiency = #simtrks assoc. to recotrk #simtrks (for signal sim tracks only) Tracking fake rate = #reco trks not assoc. to sim trk #reco trks (for “all” reco tracks) CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  32. TIB Efficiency Study • Tracking efficiency for (TIB1,2 @ 80% vs 100%), high purity tracks Using ttbar sample Look at tracking efficiency when the TIB1,2 layers are 80% efficient. Data loss implemented as a random inefficiency (simulating specific dead modules associated with possible future failed cooling lines needs to be done.) CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  33. TIB Efficiency Study • Ratio of tracking efficiency for (TIB1,2 @ 80% / TIB1,2 @ 100%) Using ttbar sample Tracking efficiency degrades much more at <PU>=50 when the TIB1,2 layers are 80% efficient. The degradation is worse for the current geometry compared to the Phase 1 geometry. We can gain about 10% per tracks in the central region. CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  34. TIB Efficiency Study • Track fake rates for TIB1,2 @ 80% and TIB1,2 @ 100% efficiency Using ttbar sample Look at tracking fake rate when the TIB1,2 layers are 80% efficient. Data loss implemented as a random inefficiency (simulating specific dead modules associated with possible future failed cooling lines needs to be done.) CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

  35. TIB Efficiency Study • Ratio of track fake rates for (TIB1,2 @ 80% / TIB1,2 @ 100%) Using ttbar sample Track fake rates also increase more at <PU>=50 when the TIB1,2 layers are 80% efficient. The increase in fake rate is higher for the current geometry compared to the Phase 1 geometry. Beware! Results will depend on tuning for tracking! CMS Upgrade Workshop, 7 Nov 2011 H. W. K. Cheung (FNAL)

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