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External Memory Interfaces

External Memory Interfaces. External Memory Interfaces. Many microcontrollers (and all microprocessors) have an external memory interface Allows adding additional memory to the micro Requires an external address/data bus PSoC has only an 8-bit RAM bus and a 16-bit Flash ROM bus

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External Memory Interfaces

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  1. External Memory Interfaces

  2. External Memory Interfaces • Many microcontrollers (and all microprocessors) have an external memory interface • Allows adding additional memory to the micro • Requires an external address/data bus • PSoC has only an 8-bit RAM bus and a 16-bit Flash ROM bus • Both already full with 256 bytes of RAM and (up to) 64KB of Flash ROM • No external bus (unless you make one with GPIO) • We’ll use the Motorola/Freescale HC11 as an example

  3. HC11 external memory interface • 8-bit data bus • Unit of transfer is a single byte • 16-bit address bus • Allows up to 64K total addresses (64K bytes) • Von Neumann architecture • One address space for all memory types, including code and data • Address space includes internal memories and space for external memories

  4. HC11-A8 Internal Address Map 0000 - 00FF Internal RAM (256 Bytes) Internal Regs (64 Bytes) 1000 - 103F Variants of the HC11 may have more/less RAM, EEROM and EPROM Empty spaces have no physical memory at all. B600 - B7FF Internal EEROM (512 Bytes) Internal ROM or EPROM(8K Bytes) E000 - FFFF

  5. Adding Memories 0000 - 00FF Add a 16K x 8 (16Kbyte) memorystarting at location $4000 1000 - 103F 16K = 214Range: 00 0000 0000 0000 -11 1111 1111 1111 External Memory(16K Bytes) 4000 – 7FFF Add to initial address of $4000 = 0100 0000 0000 0000 0100 0000 0000 0000 (4000)to 0111 1111 1111 1111 (7FFF)  01xxxxxxxxxxxxxx B600 - B7FF Internal EEROM (512 Bytes) External Memory(8K Bytes) C000 - DFFF Add an 8K x 8 (8Kbyte) memorystarting at location $C000 E000 - FFFF Internal ROM or EPROM(8K Bytes) 110x xxxx xxxx xxxx

  6. When Memory isn’t Memory • I/O devices often have a few registers • Control registers • I/O registers • If these have an interface that looks like memory, we can connect them to the memory bus • Reads/Writes to certain locations will produce the desired change in the I/O device controller • Almost all external devices can be configured to look like a memory

  7. A0-A13 D0 A0-A10 D0-D7 OE* OE* 6167 SRAM 6116P-4 SRAM CS* CS* WE* WE* Static Memories • Real SRAMs come in a variety of sizes, but are based on the same basic principles • Address input specifies where to read/write • Data input/output contains data to read or write • WE* (write enable): 1 for reads, 0 for writes • OE* (output enable): 0 enables the output drivers • CS* (chip select): 0 to select the chip (enable it) Bitwide16K x 1-bit: 20 pins Bytewide2K x 8-bit: 24 pins

  8. Bitwide vs. Bytewide • Bytewide chips provide a complete byte at a time • Perfect for microcontroller systems • Bitwide chips provide only one bit at a time • We usually need a whole byte (or more) • Requires putting eight or more chips together • Common addressing for all chips • Each chip provides a single bit • Example: 32-bit wide memory needs 32 chips • Bitwide chips make sense only when we’re going to have to use a lot of chips anyway (i.e. large systems)

  9. A0-A12 D0-D7 OE* CS1* HM6264A SRAM CS2 WE* A Simple Memory • The HM6264A SRAM is a simple memory • Static RAM • 8-bit data bus • 13-bit address bus • 213=8192 bytes • Four control signals • WE* - asserted low if this is a write • CS1*, CS2 - Chip Select • If both are asserted, enables chip • Means Address is valid • OE* - Output Enable • Allows memory to drive the data bus

  10. What memory needs... • For a memory read, we need to: • Place the address on the address pins • Assert CS1*, CS2, OE* • Wait for the memory to respond with the requested data • Look at the value on the output pins • For a memory write, we need to: • Place address on address pins • Assert CS1*, CS2, WE* • Place the data on the data pins • Hold it there for required amount of time

  11. Address Bus A00-A15 Data Bus D00-D07 D0-D7 A0-A12 VCC CS2 R/W* WE* 8Kx8SRAM AV CS1* OE* MicroProc Connecting a memory to a Microprocessor Example for a micro with separate 16-bit Address and 8-bit data busses ‘1’ for read, ‘0’ for write • How do we know where memory should be located in address space? • What about real microcontroller interfaces? ‘0’ for read, ‘1’ for write ‘1’ when address is valid ‘0’ when read/write to chip

  12. CSB* A15 A14 CSA* A13 f A12 CS* A11 CS* A10 Memory1 Memory2 A01 A00 D7 D1 D0 Selecting a Memory • How do we connect two (or more) devices without conflicting with each other? • Select only one chip at a time • Available Information for the selection process • AS, R/W*, Address (A12 – A00 go to memory chip) • Only the unused address bits (A15-A13) can help us • CSA* and CSB* should be (exclusive) functions of A15-A13

  13. AV CSA* A15 A14 A13 AV CSB* A15 A14 A13 Picking a select function CSA* asserted when A15--A13 = 001 CSB* asserted when A15--A13 = 011 CSA* will be asserted whenever address is001x xxxx xxxx xxxx which is: 0010 0000 0000 0000 - 0011 1111 1111 1111 --> $2000-$3FFF CSB* will be asserted whenever address is011x xxxx xxxx xxxx which is: 0110 0000 0000 0000 - 0111 1111 1111 1111 --> $6000-$7FFF

  14. Full Address Decoding • Full address decoding: • Look at alladdress bits when choosing which memory to select • All unused memory bits must be looked at to make sure they’re the right combination of 0’s and 1’s • Each device/memory has a unique range of addresses in the address space • Hints: • Put fixed (internal) memories in the map first • Place largest memories next • Continue down to the smallest devices

  15. (12 bits of address) 4K bytes for ROM1 Int. EPROM Int. EEROM Int. Regs x x x x x x x x x x x x x x x x x x x x x x x x 1 1 1 x x x x 1 0 1 1 0 1 1 0 0 0 1 0 0 0 0 0 0 F.A.D. Example 1 – Groupmemories together Full Address Decoding 256 bytes for Internal RAM (8 bits of address, $0000 - $00FF) Fixed (internal) memories 64 bytes for Internal Regs (6 bits of address, $1000 - $103F) 512 bytes for Internal EEROM (9 bits of address, $B600 - $B7FF) 8K bytes for Internal EPROM (13 bits of address, $E000 - $FFFF) 16K bytes for RAM (14 bits of address) $4000 - $7FFF $8000 - $8FFF 1K bytes for ROM2 (10 bits of address) $9000 - $93FF 4 bytes for ADC (2 bits of address) $9400 - $9403 2 bytes for LCD (1 bit of address) $9404 - $9405 Address Bits 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Int. RAM x x x x x x x x 0 0 0 0 0 0 0 0 x x x x x x x x x x x x x x 0 1 RAM ROM1 x x x x x x x x x x x x 1 0 0 0 x x x x x x x x x x ROM2 1 0 0 1 0 0 ADC 1 0 0 1 0 1 0 0 0 0 0 0 0 0 x x LCD 1 0 0 1 0 1 0 0 0 0 0 0 0 1 0 x

  16. Resulting Address Map 0000 - 00FF Internal RAM (256 Bytes) 1000 - 103F ROM1CS=f1(A15,A14,A13,A12) Internal Regs (64 Bytes) RAMCS=f2(A15,A14) RAM (16K Bytes)4000-7FFF ROM2CS=f3(A15,A14,A13,A12,A11,A10) ADCCS=f4(A15,A14,A13,A12,A11,A10, A9,A8,A7,A6,A5,A4 ,A3,A2) 8000 – 8FFF ROM1 (4K Bytes) 9000 - 93FF ROM2 (1K Bytes) 9400 - 9403 ADC (4 Bytes) 9404 - 9405 LCD (2 Bytes) LCDCS=f5(A15,A14,A13,A12,A11,A10, A9,A8,A7,A6,A5,A4 ,A3,A2,A1) Internal EEROM (512 Bytes) B600 - B7FF Full address decoding requires alot of inputs (lots of hardware) for small devices Internal EPROM (8K Bytes)E000-FFFF

  17. (12 bits of address) 4K bytes for ROM1 Int. EPROM Int. EEROM Int. Regs x x x x x x x x x x x x x x x x x x x x x x x x 1 1 1 x x x x 1 0 1 1 0 1 1 0 0 0 1 0 0 0 0 0 0 F.A.D. Example 2 – Placememories in lowest address Full Address Decoding 256 bytes for Internal RAM (8 bits of address, $0000 - $00FF) Fixed (internal) memories 64 bytes for Internal Regs (6 bits of address, $1000 - $103F) 512 bytes for Internal EEROM (9 bits of address, $B600 - $B7FF) 8K bytes for Internal EPROM (13 bits of address, $E000 - $FFFF) 16K bytes for RAM (14 bits of address) $4000 - $7FFF $2000 - $2FFF 1K bytes for ROM2 (10 bits of address) $0400 - $07FF 4 bytes for ADC (2 bits of address) $0100 - $0103 2 bytes for LCD (1 bit of address) $0104 - $0105 Address Bits 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Int. RAM x x x x x x x x 0 0 0 0 0 0 0 0 x x x x x x x x x x x x x x 0 1 RAM ROM1 x x x x x x x x x x x x 0 0 1 0 x x x x x x x x x x ROM2 0 0 0 0 0 1 ADC 0 0 0 0 0 0 0 1 0 0 0 0 0 0 x x LCD 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 x

  18. F.A.D. Discussion • Full Address Decoding assigns one address to each memory location • Other addresses create errors • Easy to add more devices later • Decoding addresses is complicated • Requires lots of hardware (possibly more than the memory chips themselves) • We could have only used fewer bits since there are only five external devices

  19. 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 ROM0x x x x x x x x x x x RAM 1x x x x x x x x x x x Partial Address Decoding • Place a 2KByte RAM and a 2KByte ROM in address space • Simply use highest-order bit to choose RAM/ROM (A15) • If A15 is 1, use RAM, if 0, use ROM • Requires only a single inverter • But, what about all of those unused bits (A14-A11)? • They’re “don’t cares” -- can be either 0 or 1 • Our logic won’t even look at them

  20. 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 ROM0x x x x x x x x x x x RAM 1 x x x x x x x x x x x Multiple Addresses • Consider addresses: • $1100 = 0001 0001 0000 0000 • $3100 = 0011 0001 0000 0000 • They differ only in bit A13 • But A13is a don’t care bit (it is not decoded) • We can’t tell the difference between the two • Both addresses point to the same memory location!

  21. There are 16 different combinations of bits A15, A14, A13, and A12 Thus, there are 16 aliases for each memory address Aliases for $8014: $8014 $8814 $9014 $9814 $A014 $A814 $B014 $B814 $C014 $C814 $D014 $D814 $E014 $E814 $F014 $F814 Aliases 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 ROM0x x x x x x x x x x x RAM 1 x x x x x x x x x x x From 0000 to 1111 The primary address range is the one with all the blanks filled in as zeros The total address range is the one with all the blanks filled in as x’s (either zeros or ones)  Total address range >= primary address range

  22. Partial Address Decoding • Partial address decoding: • Look at a minimum number of address bits when choosing which memory to select • All unused memory bits are left undecoded • Devices may appear in the address space multiple times (addresses may have aliases) • Strategy: • Put fixed (internal) memories in the map first • Place largest memories next Algorithm:Pick the lowest-numbered space and the minimum number of bits. Retry if you run out of space. • Decode onlyas many bits as needed • A greedy algorithm works OK

  23. (12 bits of address) 4K bytes for ROM1 Int. RAM x x x x x x x x 0 0 0 0 0 0 0 0 Int. EEROM Int. Regs Int. EPROM x x x x x x x x x x x x x x x x x x x x x x x x 1 0 1 1 0 1 1 0 0 0 1 0 0 0 0 0 0 1 1 1 x x x x Partial Address Decoding Total Range Primary Range 16K bytes for RAM (14 bits of address) $4000 - $7FFF $4000 - $7FFF (16KB) $2000 - $2FFF $2000 - $3FFF (8KB) 1K bytes for ROM2 (10 bits of address) $8000 - $83FF $8000 - $9FFF (8KB) 4 bytes for ADC (2 bits of address) $C000 - $C003 $C000 - $DFFF (8KB) 2 bytes for LCD (1 bit of address) $A000 - $A001 $A000 - $AFFF (4KB) Address Bits 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 x x x x x x x x x x x x x x 0 1 RAM ROM1 x x x x x x x x x x x x 0 0 1 x x x x x x x x x x ROM2 1 0 0 ADC 1 1 0 x x Total # of address lines decoded = 15 LCD 1 0 1 0 x

  24. ROM1 (4K Bytes) RAM (16K Bytes) 4000 - 7FFF Resulting Address Map 0000 - 00FF Internal RAM (256 Bytes) 1000 - 103F RAMCS=f2(A15,A14) Internal Regs (64 Bytes) 2000 - 3FFF ROM1CS=f1(A15,A14,A13) ROM2CS=f3(A15,A14,A13) ADCCS=f4(A15,A14,A13) LCDCS=f5(A15,A14,A13,A12) 8000 – 9FFF ROM2 (1K Bytes) LCD (2 Bytes) A000 - AFFF Internal EEROM (512 Bytes) B600 - B7FF C000 - DFFF ADC (4 Bytes) Internal EPROM (8K Bytes)E000-FFFF Partial address decoding is simple (can often be done with a single chip)However, it wastes space

  25. P.A.D. Discusion • Partial Address Decoding allows simpler decoding of the address space • Use only as many bits as needed • But, there are multiple copies of the various devices in the address space • Many different names for the same data (aliases) can be confusing • Cannot detect incorrect addresses • The multiple copies waste address space • Limit expansion

  26. 0 E Y0 0 E Y1 AV E . . . A15 C A14 ‘138 B A13 Y7 A Need to ‘OR’ two outputs together to make a 16KB block A A Negative logic OR: B B 74’138 3-to-8 decoder Using Decoders Enable when AV (address valid) is high Each output goes to CS* for a memory or other device Decode three high-order bits of address Supports up to eight different memories/devices, each up to 8KB.

  27. E E Y0 Y0 E E Y1 Y1 0 0 E E 0 . . . . . . C C AV AV ‘138 ‘138 B B A12 A15 Y7 Y7 A A A11 A14 A13 A10 Subdividing Blocks 8KB from 2000 - 3FFF Selects 8KB blocks Other lines may: Select devices Go to other decoders Assert errors Decode next three bits Eight 1KB Blocks from 2000 - 3FFF Supports up to seven 8KB memories and eight smaller devices

  28. (12 bits of address) 4K bytes for ROM1 Int. RAM x x x x x x x x 0 0 0 0 0 0 0 0 Int. Regs Int. EEROM Int. EPROM x x x x x x x x x x x x x x x x x x x x x x x x 1 0 1 1 0 1 1 0 0 0 1 0 0 0 0 0 0 1 1 1 x x x x Address Decoding with 3-to-8 Decoders Total Range Primary Range 16K bytes for RAM (14 bits of address) $4000 - $7FFF $4000 - $7FFF (16KB) $2000 - $2FFF $2000 - $3FFF (8KB) 1K bytes for ROM2 (10 bits of address) $8000 - $83FF $8000 - $83FF (1KB) 4 bytes for ADC (2 bits of address) $8400 - $8403 $8400 - $87FF (1KB) 2 bytes for LCD (1 bit of address) $8800 - $8801 $8800 - $8BFF (1KB) Address Bits 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 x x x x x x x x x x x x x x 0 1 RAM Need to OR two blocks together ROM1 x x x x x x x x x x x x 0 0 1 x x x x x x x x x x ROM2 1 0 0 0 0 0 ADC 1 0 0 0 0 1 x x LCD 1 0 0 0 1 0 x Decoder 1 Decoder 2

  29. 0 Y0 E ROM1CS* 0 Y1 E Y2 AV ROM1 (4K Bytes) E Y3 Y4 A15 Y5 C A14 Y6 ‘138 B A13 Y7 A RAM (16K Bytes) RAMCS* 4000 - 7FFF ROM2CS* Y0 E ADCCS* Y1 0 E Y2 LCDCS* AV Y3 E Y4 A12 Y5 C A11 Y6 ‘138 B A10 Y7 A Resulting Address Map – Block Decoding 0000 - 00FF Internal RAM (256 Bytes) 1000 - 103F Internal Regs (64 Bytes) 2000 - 3FFF ROM2 (1K Bytes) 8000 - 83FF ADC (4 Bytes) 8400 – 87FF LCD (2 Bytes) 8800 – 8BFF Internal EEROM (512 Bytes) B600 - B7FF Internal EPROM (8K Bytes)E000-FFFF Using decoders is simple and efficient

  30. HC11 Memory Interface • Address Bus • 16 bits - A15 to A00 • 216bytes addressable by memory bus • Data Bus • 8 bits - D07 to D00 • Bi-directional - for reads from memory, or writes to memory • Multiplexed together • A07-A00 are shared with D07-D00 • Address comes first, then data

  31. R/W or R/W* - Read/Write • 1 indicates bus is performing a read operation • 0 indicates bus is performing a write operation HC11 Memory Control Interface • AS - Address Strobe • Indicates that the contents of the address bus are valid • E Clock • Symmetric clock running at 1/4 the speed of the external clock • Memory interface is synchronized with the E clock

  32. 0 Y0 E 0 Y1 E Y2 E Y3 A15 Y4 74’138Decoder A14 C Y5 Y6 ‘138 B A13 Y7 A 1 E CS1* CS2 R/W* 0 OE* A12-A8 WE* A15-A08 A12-A0 A12-A0 68HC11A8 0 HM6264A SRAM AS Clk OE* D7-D0 A7-A0 Q7-Q0 D7-D0 74’373 Latch A/D7-A/D0 Connecting SRAM memory to the HC11 Addresses:$6000-$7FFF 6264 will work with OE*permanently asserted

  33. Data (from memory) A00-A12 (latch output) Address Valid CS1* (decoder output) E CLK Read takesone clock cycle R/W* A15-A8 Memory provides data some time after selected by CS1* Address(from CPU) A/D Bus CPU reads data at end of clock cycle HC11 Read Operation AS AS: Indicates Address valid – used to latch A7-A0 CS1* generated by address decoder – selects memory. Decoder enabled by E clock.

  34. setuptime holdtime D Q D Q Clk Setup and Hold Times Setup Time: How long a signal must be stable preceding the clock edge Hold Time: How long a signal must be stable after the clock edge Clk D Setup: PassHold: Pass Setup: FailHold: Pass Setup: PassHold: Fail Setup: Fail Hold: Fail

  35. HC11 Bus Timing (Read) tcyc PWEL PWEH tr tf E CLK tAH R/W* tAV A15-A8 tACCA tDSR tAVM tACCE tDHR tMAD A/DMultiplexed Address(from CPU) Data (from memory) tASL tAHL AS tASD PWASH tASED Times for a2MHz E clock Parameter Min Max These params describe HC11’s outputs Tcyc Cycle time 500ns PWEL Pulse width, E low 227ns must total to Tcyc PWEH Pulse width, E high 222ns tr,tf Rise time, fall time for E clock 20ns

  36. HC11 Bus Timing (Read) tcyc PWEL PWEH tr tf E CLK tAH R/W* tAV A15-A8 tACCA tDSR tAVM tACCE tDHR tMAD A/DMultiplexed Address(from CPU) Data (from memory) tASL tAHL AS tASD PWASH tASED Times for a2MHz E clock Parameter Min Max These params describe HC11’s outputs TMAD Muxed address delay 83ns TAV Non-muxed address valid ‘til E 94ns TAVM Muxed address valid ‘til E 84ns tAH Address hold time 33ns

  37. HC11 Bus Timing (Read) tcyc PWEL PWEH tr tf E CLK tAH R/W* tAV A15-A8 tACCA tDSR tAVM tACCE tDHR tMAD A/DMultiplexed Address(from CPU) Data (from memory) tASL tAHL AS tASD PWASH tASED Times for a2MHz E clock Parameter Min Max These params describe HC11’s outputs tASD Address strobe delay from E 53ns PWASH Pulse width address strobe high 96ns tASED Address strobe to E clock delay 53ns AS is useful for latching the address tASL Muxed address valid to strobe low 26ns tAHL Muxed address hold time 33ns

  38. HC11 Bus Timing (Read) tcyc PWEL PWEH tr tf E CLK tAH R/W* tAV A15-A8 tACCA tDSR tAVM tACCE tDHR tMAD A/DMultiplexed Address(from CPU) Data (from memory) tASL tAHL AS tASD PWASH tASED Times for a2MHz E clock These params must be satisfied by mem interface Parameter Min Max tACCA HC11 Address access time 307ns tACCE HC11 access time 192ns 192+30 = 222= PWEH tDSR Data setup time (read) 30ns tDHR Data hold time (read) 0ns 83ns

  39. tRC 6264A Read Cycle tAA A00-A12 Address Valid tCO1 CS1* tLZ1 tHZ1 tHZ2 tCO2 CS2 tLZ2 OE* tOH tOE tOHZ D0D7 Data Valid tOLZ Parameter Min Max tRC Read Cycle time 120ns tAA Address Access time 120ns If OE* is tied low, then use tCO1,2 and tLZ1,2 tC01,2 CS1,2 to data valid 120ns tLZ1,2 CS1,2 to data bus driven 10ns tOLZ Output enable to data bus driven 5ns tOE Output enable to data valid 60ns tOH Output hold after address change 10ns tHZ1,2 CS1,2 unasserted to data Hi-Z 0ns 40ns

  40. PWEL PWEH t138 t373 t138 tAA A00-A12 (latch output) Address Valid tCO1 CS1* (decoder output) E CLK tAH R/W* tAV A15-A8 tACCA tDSR tOH tAVM tACCE tDHR tMAD Address(from CPU) Data (from memory) A/D Bus tLZ1 tASL tAHL Combined Circuit Timing tHZ1 AS tASD PWASH tASED t373: 74’373 delay from clock to output t138: 74’138 delay from enable to output

  41. What to Analyze • Read Setup Time • Does the data from the memory come back early enough to be clocked in by the HC11 properly? • Read Hold Time • Is the data from the memory held long enough after the clock to be clocked properly? • Bus Conflicts • Are there any times that more than one device is driving the same bus? • Specifically, do the memory drivers go to Hi-Z before the HC11 puts the address on the A/D bus?

  42. PWEL PWEH A00-A12 (latch output) Address Valid E CLK tAH R/W* tAV A15-A8 tACCA tDSR tOH tAVM tACCE tDHR tMAD Address(from CPU) Data (from memory) A/D Bus tLZ1 tASL tAHL Read Setup Time From CS1* tHZ1 AS tASD PWASH tASED t138 t373 t138 tAA tCO1 CS1* (decoder output) tDSR: Minimum setup time req’d by HC11 Actual Setup Time: PWEH –(t138+ tC01)

  43. PWEL PWEH A00-A12 (latch output) Address Valid E CLK tAH R/W* tAV A15-A8 tACCA tDSR tOH tAVM tACCE tDHR tMAD Address(from CPU) Data (from memory) A/D Bus tLZ1 tASL tAHL tHZ1 Read Setup Time from Address AS tASD PWASH tASED t138 t373 t138 tAA tCO1 CS1* (decoder output) tDSR: Min setup time Actual Setup Time: PWEH + tASED+ PWASH – (t373+ tAA)

  44. PWEL PWEH E CLK tAH R/W* tAV A15-A8 tACCA tDSR tOH tAVM tACCE tDHR tMAD Address(from CPU) Data (from memory) A/D Bus tLZ1 tASL tAHL tHZ1 Read Hold Time Analysis (min) AS tASD PWASH tASED t138 t373 t138 tAA A00-A12 (latch output) Address Valid tCO1 CS1* (decoder output) Minimum Req’d Hold Time: tDHR(min) Actual min Hold Time: tAH+ tOH

  45. PWEL PWEH E CLK tAH R/W* tAV A15-A8 tACCA tDSR tOH tAVM tACCE tDHR tMAD Address(from CPU) Data (from memory) A/D Bus tLZ1 tASL tAHL tHZ1 Read Hold Time Analysis (max) AS tASD PWASH tASED t138 t373 t138 tAA A00-A12 (latch output) Address Valid tCO1 CS1* (decoder output) Max allowed Hold Time: tDHR(max) Actual max Hold Time: t138 + tHZ1(max)

  46. Checking Setup/Hold Times (2 MHz HC11) Data setup time from Chip Select Data setup time from Address Valid PWEH – (t138 + tC01)>tDSR PWEH + tASED+ PWASH – (t373 + tAA) > tDSR 222 – (8 + 120 ns) > 30 ns 222 + 53 + 96 – (11.5 + 120 ns) > 30 ns   239.5 ns > 30 ns 94 ns > 30 ns Data held on bus long enough Data not held on bus too long tDHR(min) < tAH+ tOH t138 + tHZ1(max) < tDHR(max) 0 ns < 33 + 10 ns 8 + 40ns < 83 ns   0 ns < 43ns 48ns < 83 ns

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