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Single Event Effects of a 0.15µm Antifuse FPGA

Single Event Effects of a 0.15µm Antifuse FPGA. J. J. Wang, Brian Cronquist, John McCollum, Solomon Wolday, Minal Sawant Actel Corporation Rich Katz, Igor Kleyner (OSC) - NASA/GSFC. Outline. Device and Architecture Heavy Ion Beam Test Test Results SEE Hardening Conclusion.

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Single Event Effects of a 0.15µm Antifuse FPGA

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  1. Single Event Effects of a 0.15µm Antifuse FPGA J. J. Wang, Brian Cronquist, John McCollum, Solomon Wolday, Minal Sawant Actel Corporation Rich Katz, Igor Kleyner (OSC) - NASA/GSFC

  2. Outline • Device and Architecture • Heavy Ion Beam Test • Test Results • SEE Hardening • Conclusion JJ Wang, Paper C2, MAPLD2002

  3. Device Family • 0.15µm/1.5V CMOS technology, 7 layer metal. • High capacity (2 million system gate), non-volatile solution. • High performance (350MHz system), PLL conditioned clock. • Flexible I/O. • Easy place-and-route, high utilization close to 100%. • High security, preventing reverse engineering. JJ Wang, Paper C2, MAPLD2002

  4. Device Architecture – Antifuse Switch • Sea of module • Metal-insulator-metal antifuse • Very high density of antifuse switches, easy place-and-route JJ Wang, Paper C2, MAPLD2002

  5. Device Architecture - AX1000 • User logic: fully fracturable super cluster (combinatorial cell + register cell), embedded SRAM block. • Fast, bank-selectable I/O supporting mixed voltage and different standards • High performance routing; (C to adjacent R ) < 0.1ns. • Segmentable clock conditioned by PLL; input freq=14MHz - 200MHz, output freq=20MHz-1GHz. JJ Wang, Paper C2, MAPLD2002

  6. Device Architecture - I/O • Flexible I/O supporting mixed voltage 1.5, 1.8, 2.5, 3.3V, and 14 single-ended, differential, or voltage-referenced standards. • Organized into (8) banks, each bank independently configured. • Unique 64-bit, bidirectional PerPin I/O FIFO. JJ Wang, Paper C2, MAPLD2002

  7. Device Architecture – Routing • High performance local routing in and between super-clusters; Fast-Connect, Direct-Connect and Carry-Connect, • Within core tile routing between super-clusters; vertical and horizontal tracks running across rows and columns respectively. • Chip level routing supported by device length, segmented and non-segmented, vertical and horizontal tracks running both north-to-south and east-to-west. JJ Wang, Paper C2, MAPLD2002

  8. Device Architecture - Clock • 8 segmentable global clocks; 4 hard-wired (HCLK), 4 routed (CLK). • Accepting locally generated signals. • MUX extensively used at every routing level. • Very flexible, supporting large number of local clocks; 24 segments for each HCLK driving north-south, and 28 segments for each CLK driving east-west. • Many branches and leafs with small capacitive loads susceptible to single event error. JJ Wang, Paper C2, MAPLD2002

  9. Device Architecture – Embedded SRAM • Each RAM block with 4608 bits. • Dedicated FIFO control logic to generate internal addresses and external flag (FULL, EMPTY, AFULL, AEMPTY). • Able to cascade up to 16 RAM blocks. • High density, small-sized features susceptible to single event error. JJ Wang, Paper C2, MAPLD2002

  10. Preliminary Total Ionizing Dose Test • Irradiated by gamma statically biased (VCCI/VCCA = 3.3V/1.5V) at room temperature. • Dose rate = 33 rads(Si)/sec. • Total accumulated dose to 200 krads(Si)/sec. • No change in propagation delay. • No change in ICCA. • ICCI increased from 1.2 mA to 8 mA. JJ Wang, Paper C2, MAPLD2002

  11. Heavy-Ion Beam Test JJ Wang, Paper C2, MAPLD2002

  12. SEE Test Results - Summary • SEU (Single Event Upset) • SRAM (Static Mode) • LETTH ~1.4 MeV-cm2/mg • Register cell • 3.36 > LETTH > 2.89 MeV-cm2/mg • Clock upset • 11.4 > LETTH > 6.73 MeV-cm2/mg • Control logic upset, a.k.a. SEFI (Single Event Functional Interrupt) • 11.4 > LETTH > 6.73 MeV-cm2/mg • In power up reset circuit • No SEL up to LET = 120 MeV-cm2/mg • No SEDR up to LET = 120 MeV-cm2/mg, need more tests to confirm JJ Wang, Paper C2, MAPLD2002

  13. SEU Results - SRAM • Weibull curve parameters: s=3.5x10-8 cm2, L0=1.44 MeV-cm2/mg, Width=15 MeV-cm2/mg, Shape=1. • Collection depth=0.5µm obtained by calibrating test data with SPICE simulation, assuming worst-case no funneling. • SEU rate=2.93x10-7 upset/bit-day at GEO MIN, with 25 mil Al shielding (Space Radiation 4.5). JJ Wang, Paper C2, MAPLD2002

  14. SRAM SEU Hardening by EDAC • R. Baumann, SEE Symposium 2002. • Hamming code can detect 2 bits error, correct 1 bit error. • Layout of bits in one word has to be scrambled to avoid single event MBU (multiple bit upset). JJ Wang, Paper C2, MAPLD2002

  15. SRAM SEU Hardening by EDAC • IP (Intellectual Property) Hamming encoder/decoder. • The longer the refresh cycle time, the higher MBU error rate. • MBU rate calculated from single bit SEU rate predicted from test data. • Optional sweeper available for periodic data refresh to reduce static error rate potential. JJ Wang, Paper C2, MAPLD2002

  16. SEU Results – R-cell • Weibull curve parameters: s=1.0x10-6 cm2, L0=3.0 MeV-cm2/mg, Width=30 MeV-cm2/mg, Shape=2. • Collection depth=0.5µm, assuming worst-case no funneling. • SEU rate=9.96x10-7 upset/bit-day at GEO MIN, with 25 mil Al shielding (Space Radiation 4.5). JJ Wang, Paper C2, MAPLD2002

  17. SEU Results – R-cell • Zeros pattern may be slightly more sensitive than Ones pattern. JJ Wang, Paper C2, MAPLD2002

  18. SEU Results – Clock Upset No clock upset • Detectable only by checkerboard pattern. • 11.4 > LETTH > 6.73 MeV-cm2/mg. • Saturation cross section ~ 1x10-5 cm2 (1000 µm2). JJ Wang, Paper C2, MAPLD2002

  19. Clock Upset – Spice Simulation and Hardening Node at state 'High' for NMOS strike Heavy Ion Strike OUT VCC 0 VCC 0 • Many sensitive nodes identified. • Sensitive node with LETTH ~ 9 MeV-cm2/mg found by SPICE simulation (collection depth=0.5 µm). • Hardening by redundancy and sizing. JJ Wang, Paper C2, MAPLD2002

  20. SEU Results – Control Logic Upset • Burst of errors overflows the counter. • Zero pattern is least sensitive, only one occurrence at LET=37.45 MeV-cm2/mg. • Power up reset circuit using storage devices to reset R-cells to zero. • Lowest LET detectable between 11.4 and 6.73 MeV-cm2/mg. JJ Wang, Paper C2, MAPLD2002

  21. Conclusions • When compared to the 0.25 µm SXA device, the scaling of feature size and supply voltage in the 0.15 µm device significantly enhanced the SEU/SET susceptibility while reducing the SEL and SEDR susceptibility. • High performance and flexible features also increase SEU/SET susceptibility, e. g. MUXs in the clock tree. • Hardening by EDAC/IP, redundancy, and sizing is feasible to eliminate hard error (control logic upset) and reduce the soft error (SRAM upset, R-cell upset, clock upset, SET induced upset). JJ Wang, Paper C2, MAPLD2002

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