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Fundamentals of Digital Test and DFT

This course covers basic concepts and definitions of digital test and Design for Testability (DFT). Topics include fault modeling, fault simulation, ATPG, DFT and scan design, BIST, boundary scan, and IDDQ test. The course also explores the cost and challenges of testing in the manufacturing process.

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Fundamentals of Digital Test and DFT

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  1. Fundamentals of Digital Test and DFT Vishwani D. Agrawal Rutgers University, Dept. of ECE New Jersey http://cm.bell-labs.com/cm/cs/who/va January 2003 Agrawal: Digital Test and DFT

  2. Course Outline • Basic concepts and definitions • Fault modeling • Fault simulation • ATPG • DFT and scan design • BIST • Boundary scan • IDDQ test Agrawal: Digital Test and DFT

  3. VLSI Realization Process Customer’s need Determine requirements Write specifications Design synthesis and Verification Test development Fabrication Manufacturing test Chips to customer Agrawal: Digital Test and DFT

  4. Definitions • Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes. • Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function. • Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect. Agrawal: Digital Test and DFT

  5. Realities of Tests • Based on analyzable fault models, which may not map onto real defects. • Incomplete coverage of modeled faults due to high complexity. • Some good chips are rejected. The fraction (or percentage) of such chips is called the yield loss. • Some bad chips pass tests. The fraction (or percentage) of bad chips among all passing chips is called the defect level. Agrawal: Digital Test and DFT

  6. Costs of Testing • Design for testability (DFT) • Chip area overhead and yield reduction • Performance overhead • Software processes of test • Test generation and fault simulation • Test programming and debugging • Manufacturing test • Automatic test equipment (ATE) capital cost • Test center operational cost Agrawal: Digital Test and DFT

  7. Cost of Manufacturing Testing in 2000AD • 0.5-1.0GHz, analog instruments,1,024 digital pins: ATE purchase price • = $1.2M + 1,024 x $3,000 = $4.272M • Running cost (five-year linear depreciation) • = Depreciation + Maintenance + Operation • = $0.854M + $0.085M + $0.5M • = $1.439M/year • Test cost (24 hour ATE operation) • = $1.439M/(365 x 24 x 3,600) • = 4.5 cents/second Agrawal: Digital Test and DFT

  8. Present and Future* 1997--2001 2003--2006 Feature size (micron) 0.25 - 0.15 0.13 - 0.10 Transistors/sq. cm 4 - 10M 18 - 39M Pin count 100 - 900 160 - 1475 Clock rate (MHz) 200 - 730 530 - 1100 Power (Watts) 1.2 - 61 2 - 96 * SIA Roadmap, IEEE Spectrum, July 1999 Agrawal: Digital Test and DFT

  9. Method of Testing Agrawal: Digital Test and DFT

  10. ADVANTEST Model T6682 ATE Agrawal: Digital Test and DFT

  11. LTX FUSION HF ATE Agrawal: Digital Test and DFT

  12. VLSI Chip Yield • A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the fabrication process. • A chip with no manufacturing defect is called a good chip. • Fraction (or percentage) of good chips produced in a manufacturing process is called the yield. Yield is denoted by symbol Y. • Cost of a chip: Cost of fabricating and testing a wafer -------------------------------------------------------------------- Yield x Number of chip sites on the wafer Agrawal: Digital Test and DFT

  13. Defect Level or Reject Ratio • Defect level (DL) is the ratio of faulty chips among the chips that pass tests. • DL is measured as parts per million (ppm). • DL is a measure of the effectiveness of tests. • DL is a quantitative measure of the manufactured product quality. For commercial VLSI chips a DL greater than 500 ppm is considered unacceptable. Agrawal: Digital Test and DFT

  14. Example: SEMATECH Chip • Bus interface controller ASIC fabricated and tested at IBM, Burlington, Vermont • 116,000 equivalent (2-input NAND) gates • 304-pin package, 249 I/O • Clock: 40MHz, some parts 50MHz • 0.45m CMOS, 3.3V, 9.4mm x 8.8mm area • Full scan, 99.79% fault coverage • Advantest 3381 ATE, 18,466 chips tested at 2.5MHz test clock • Data obtained courtesy of Phil Nigh (IBM) Agrawal: Digital Test and DFT

  15. Computed DL 237,700 ppm (Y = 76.23%) Defect level in ppm Stuck-at fault coverage (%) Agrawal: Digital Test and DFT

  16. Summary: Introduction • VLSI Yield drops as chip area increases; low yield means high cost • Fault coverage measures the test quality • Defect level (DL) or reject ratio is a measure of chip quality • DL can be determined by an analysis of test data • For high quality: DL < 500 ppm, fault coverage ~ 99% Agrawal: Digital Test and DFT

  17. Fault Modeling Agrawal: Digital Test and DFT

  18. Why Model Faults? • I/O function tests inadequate for manufacturing (functionality versus component and interconnect testing) • Real defects (often mechanical) too numerous and often not analyzable • A fault model identifies targets for testing • A fault model makes analysis possible • Effectiveness measurable by experiments Agrawal: Digital Test and DFT

  19. Some Real Defects in Chips • Processing defects • Missing contact windows • Parasitic transistors • Oxide breakdown • . . . • Material defects • Bulk defects (cracks, crystal imperfections) • Surface impurities (ion migration) • . . . • Time-dependent failures • Dielectric breakdown • Electromigration • . . . • Packaging failures • Contact degradation • Seal leaks • . . . Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation - Semiconductor Devices and Circuits, Wiley, 1981. Agrawal: Digital Test and DFT

  20. Observed PCB Defects Occurrence frequency (%) 51 1 6 13 6 8 5 5 5 Defect classes Shorts Opens Missing components Wrong components Reversed components Bent leads Analog specifications Digital logic Performance (timing) Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985. Agrawal: Digital Test and DFT

  21. Common Fault Models • Single stuck-at faults • Transistor open and short faults • Memory faults • PLA faults (stuck-at, cross-point, bridging) • Functional faults (processors) • Delay faults (transition, path) • Analog faults • For more examples, see Section 4.4 (p. 60-70) of the book. Agrawal: Digital Test and DFT

  22. Single Stuck-at Fault • Three properties define a single stuck-at fault • Only one line is faulty • The faulty line is permanently set to 0 or 1 • The fault can be at an input or output of a gate • Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults Faulty circuit value Good circuit value j c 0(1) s-a-0 d a 1(0) g h 1 z i 0 1 e b 1 k f Test vector for h s-a-0 fault Agrawal: Digital Test and DFT

  23. Fault Equivalence • Number of fault sites in a Boolean gate circuit = #PI + #gates + #(fanout branches). • Fault equivalence: Two faults f1 and f2 are equivalent if all tests that detect f1 also detect f2. • If faults f1 and f2 are equivalent then the corresponding faulty functions are identical. • Fault collapsing: All single faults of a logic circuits can be divided into disjoint equivalence subsets, where all faults in a subset are mutually equivalent. A collapsed fault set contains one fault from each equivalence subset. Agrawal: Digital Test and DFT

  24. Equivalence Example sa0 sa1 Faults in red removed by equivalence collapsing sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 20 Collapse ratio = ----- = 0.625 32 Agrawal: Digital Test and DFT

  25. Summary: Fault Models • Fault models are analyzable approximations of defects and are essential for a test methodology. • For digital logic single stuck-at fault model offers best advantage of tools and experience. • Many other faults (bridging, stuck-open and multiple stuck-at) are largely covered by stuck-at fault tests. • Stuck-short and delay faults and technology-dependent faults require special tests. • Memory and analog circuits need other specialized fault models and tests. Agrawal: Digital Test and DFT

  26. Fault Simulation Agrawal: Digital Test and DFT

  27. Problem and Motivation • Fault simulation Problem: Given • A circuit • A sequence of test vectors • A fault model • Determine • Fault coverage - fraction (or percentage) of modeled faults detected by test vectors • Set of undetected faults • Motivation • Determine test quality and in turn product quality • Find undetected fault targets to improve tests Agrawal: Digital Test and DFT

  28. Fault simulator in a VLSI Design Process Verification input stimuli Verified design netlist Fault simulator Test vectors Modeled fault list Test compactor Remove tested faults Delete vectors Low Fault coverage ? Test generator Add vectors Adequate Stop Agrawal: Digital Test and DFT

  29. Fault Simulation Scenario • Circuit model: mixed-level • Mostly logic with some switch-level for high-impedance (Z) and bidirectional signals • High-level models (memory, etc.) with pin faults • Signal states: logic • Two (0, 1) or three (0, 1, X) states for purely Boolean logic circuits • Four states (0, 1, X, Z) for sequential MOS circuits • Timing: • Zero-delay for combinational and synchronous circuits • Mostly unit-delay for circuits with feedback Agrawal: Digital Test and DFT

  30. Fault Simulation Scenario (continued) • Faults: • Mostly single stuck-at faults • Sometimes stuck-open, transition, and path-delay faults; analog circuit fault simulators are not yet in common use • Equivalence fault collapsing of single stuck-at faults • Fault-dropping -- a fault once detected is dropped from consideration as more vectors are simulated; fault-dropping may be suppressed for diagnosis • Fault sampling -- a random sample of faults is simulated when the circuit is large Agrawal: Digital Test and DFT

  31. Essence of Fault Sim. Test vectors Fault-free circuit Comparator f1 detected? • Disadvantage: Much repeated computation; CPU time prohibitive for VLSI circuits • Alternative: Simulate many faults together Circuit with fault f1 Comparator f2 detected? Circuit with fault f2 Comparator fn detected? Circuit with fault fn Agrawal: Digital Test and DFT

  32. Fault Sampling • A randomly selected subset (sample) of faults is simulated. • Measured coverage in the sample is used to estimate fault coverage in the entire circuit. • Advantage: Saving in computing resources (CPU time and memory.) • Disadvantage: Limited data on undetected faults. Agrawal: Digital Test and DFT

  33. Random Sampling Model Detected fault Undetected fault All faults with a fixed but unknown coverage Random picking Np = total number of faults (population size) C = fault coverage (unknown) Ns = sample size Ns << Np c = sample coverage (a random variable) Agrawal: Digital Test and DFT

  34. Probability Density of Sample Coverage, c (x--C )2 -- ------------ 1 2s2 p (x ) = Prob(x < c < x +dx ) = -------------- e s (2 p)1/2 C (1 - C) Variance, s 2 = ------------ Ns Sampling error s s p (x ) Mean = C x 1.0 C +3s C -3s x C Sample coverage Agrawal: Digital Test and DFT

  35. Sampling Error Bounds C (1 - C ) | x - C | = 3 [ -------------- ]1/2 Ns Solving the quadratic equation for C, we get the 3-sigma (99.7% confidence) estimate: 4.5 C3s = x ------- [1 + 0.44 Nsx (1 - x )]1/2 Ns Where Ns is sample size and x is the measured fault coverage in the sample. Example: A circuit with 39,096 faults has an actual fault coverage of 87.1%. The measured coverage in a random sample of 1,000 faults is 88.7%. The above formula gives an estimate of 88.7% 3%. CPU time for sample simulation was about 10% of that for all faults. Agrawal: Digital Test and DFT

  36. Summary: Fault Sim. • Fault simulator is an essential tool for test development. • Concurrent fault simulation algorithm offers the best choice. • For restricted class of circuits (combinational and synchronous sequential with only Boolean primitives), differential algorithm can provide better speed and memory efficiency (Section 5.5.6.) • For large circuits, the accuracy of random fault sampling only depends on the sample size (1,000 to 2,000 faults) and not on the circuit size. The method has significant advantages in reducing CPU time and memory needs of the simulator. Agrawal: Digital Test and DFT

  37. Automatic Test-pattern Generation (ATPG) Agrawal: Digital Test and DFT

  38. Functional vs. Structural ATPG Agrawal: Digital Test and DFT

  39. Functional vs. Structural(Continued) • Functional ATPG – generate complete set of tests for circuit input-output combinations • 129 inputs, 65 outputs: • 2129 = 680,564,733,841,876,926,926,749, 214,863,536,422,912 patterns • Using 1 GHz ATE, would take 2.15 x 1022 years • Structural test: • No redundant adder hardware, 64 bit slices • Each with 27 faults (using fault equivalence) • At most 64 x 27 = 1728 faults (tests) • Takes 0.000001728 s on 1 GHz ATE • Designer gives small set of functional tests – augment with structural tests to boost coverage to 98+ % Agrawal: Digital Test and DFT

  40. Random-Pattern Generation • Flow chart for method • Use to get tests for 60-80% of faults, then switch to D-algorithm or other ATPG for rest Agrawal: Digital Test and DFT

  41. Path Sensitization Method Circuit Example • Fault Activation • Fault Propagation • Line Justification Agrawal: Digital Test and DFT

  42. Path Sensitization Method Circuit Example • Try path f – h – k – L blocked at j, since there is no way to justify the 1 on i 1 D D D D 1 D 0 1 1 Agrawal: Digital Test and DFT

  43. Path Sensitization Method Circuit Example • Try simultaneous paths f – h – k – L and g – i – j – k – L blocked at k because D-frontier (chain of D or D) disappears 1 D D 1 1 D D D Agrawal: Digital Test and DFT

  44. Path Sensitization Method Circuit Example • Final try: pathg – i – j – k – L – test found! 0 0 D D 1 D D D 1 1 Agrawal: Digital Test and DFT

  45. Sequential Circuits • A sequential circuit has memory in addition to combinational logic. • Test for a fault in a sequential circuit is a sequence of vectors, which • Initializes the circuit to a known state • Activates the fault, and • Propagates the fault effect to a primary output • Methods of sequential circuit ATPG • Time-frame expansion methods • Simulation-based methods Agrawal: Digital Test and DFT

  46. Concept of Time-Frames • If the test sequence for a single stuck-at fault contains n vectors, • Replicate combinational logic block n times • Place fault in each block • Generate a test for the multiple stuck-at fault using combinational ATPG with 9-valued logic Vector -n+1 Vector -1 Vector 0 Fault Unknown or given Init. state Next state State variables Time- frame 0 Time- frame -n+1 Time- frame -1 Comb. block PO -1 PO 0 PO -n+1 Agrawal: Digital Test and DFT

  47. An Example of Seq. ATPG FF1 B A FF2 s-a-1 Agrawal: Digital Test and DFT

  48. Nine-Valued Logic (Muth)0,1, 1/0, 0/1,1/X, 0/X, X/0, X/1, X A 0 A X s-a-1 s-a-1 X/1 0/1 0/X 0/X X FF1 FF1 0/1 X X/1 FF2 FF2 B B X 0/1 Time-frame 0 Time-frame -1 Agrawal: Digital Test and DFT

  49. Seq. ATPG Results s1423 s5378 s35932 Total faults 1,515 4,603 39,094 Detected faults 1,414 3,639 35,100 Fault coverage 93.3% 79.1% 89.8% Test vectors 3,943 11,571 257 CPU time 1.3 hrs. 37.8 hrs. 10.2 hrs. HP J200 256MB Ref.: M. S. Hsiao, E. M. Rudnick and J. H. Patel, “Dynamic State Traversal for Sequential Circuit Test Generation,” ACM Trans. on Design Automation of Electronic Systems (TODAES), vol. 5, no. 3, July 2000. Agrawal: Digital Test and DFT

  50. Summary: ATPG • Combinational ATPG is significantly more efficient than sequential ATPG. • Combinational ATPG tools are commercially available. • Design for testability is essential if the circuit is large (million or more gates) and high fault coverage (~95%) is required. Agrawal: Digital Test and DFT

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