1. Application of Addition Algorithms Joe Cavallaro

2. Overview • Addition algorithms – core operation • Fixed-point core algorithms easy to implement • Basic adder design from full adder cell • Ripple carry addition – O(n) • Carry propagation bottleneck • “Fast” algorithms control carry transport

3. Wireless Communications Applications • Key to all matrix algorithms. • GPP and DSP processors use a given algorithm • Flexible choice in ASIC and FPGA designs • Multiuser Detection – Addition bottleneck since multiplications can be eliminated via hard decisions • Area-time complexity in choice of Adders

4. Redundant Arithmetic and On-Line Addition • Traditional number systems have “0” and “1” and work from LSB to MSB. • Redundant arithmetic allows “-1”, “0” and “1” bits per digit – implies multiple representations and “error correction” • On-Line arithmetic is bit serial from MSB to LSB • Allows for efficient pipelines and allows quick sign detection • Challenge is to quantify speedup

5. Adder Equations • Full Adder Cell • S_I = x_I XOR y_I XOR c_I • C_I+1 = x_I AND y_I OR c_I AND (x_I OR y_I)

6. Ripple Carry Adder

7. Carry look-ahead Adder

8. (f,r) Gate Tree

9. Tree Structure Adder – T > log 2n

10. Manchester Carry Chain

11. Carry Skip Adder – comparable to CLA

12. Counter Cell – Multi-operand -> Multiplication

13. Carry-Save Adders • Basic cell generate c and s output • S = (x + y + z) mod 2 • C = ((x + y + z) – s) / 2 • Final carry-propagate adder at bottom of tree

14. Carry Save Adder – 4 Operands

15. Carry Save Adder Tree for 6 Operands

16. Levels in the CSA Tree

17. Pipelined Design

18. Timing Diagram for Pipeline

19. Summary • Overview of addition algorithms • Block structures for RCA, CLA, CSA • Introduction to Redundant arithmetic and On-line arithmetic • Application to ASICs for Multiuser Detection • Reference: Israel Koren