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ECE2030 Introduction to Computer Engineering Lecture 18: Instruction Set Architecture PowerPoint Presentation
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ECE2030 Introduction to Computer Engineering Lecture 18: Instruction Set Architecture

ECE2030 Introduction to Computer Engineering Lecture 18: Instruction Set Architecture

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ECE2030 Introduction to Computer Engineering Lecture 18: Instruction Set Architecture

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  1. ECE2030 Introduction to Computer EngineeringLecture 18: Instruction Set Architecture Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech

  2. Programming in High-Level Language Compiler/Assembler/ Linker Problem Algorithms Target Machine (one implementation) System architecture Micro-architecture Functional units/ Data Path Human Level System Level RTL Level Gates Level Design Logic Level Circuit Level Silicon Level Transistors Manufacturing Breakdown of a Computing Problem Instruction Set Architecture (ISA)

  3. Instruction Set Architecture (ISA) • An abstraction • Interface between hardware and low-level software • Alleviate programmers from specifying control signals to harness a machine • Defined by • An Instruction Set • Software convention • Independent from a specific internal implementation (microarchitecture + system architecture)

  4. ISA design principles • Compatibility • Implementability • Programmability • Usability • Encoding efficiency main() { int i,b,c,a[10]; for (i=0; i<10; i++)… a[2] = b + c*i; } High Level Language Compiler … lw r2, mem[r7] add r3, r4, r2 st r3, mem[r8] ISA Binary code Assembler

  5. General Purpose Computer Von Neumann Machine Memory 0101 1001 1010 1001 1000 0100 1000 1110 1111 0011 0010 1011 1000 …… …… A stored-program computer called EDVAC proposed in 1944 while developing ENIAC, first general purpose computer Contributors: Presper Eckert John Mauchly John von Neumann EDSAC built by Maurice Wilkes implements the first operational stored-program machine Data & Instruction Data Central Processing Unit (CPU)

  6. Basic Operation 1000 1100 1110 0010 0000 0000 0000 0000 (= lw R2, mem[R7]) Instruction fetch from memory Instruction Decoder/ Microcode ROM It’s called HarvardArchitecture (Mark-III/IV) if instruction and data memory are separated Datapath Unit Data written back to memory MICROPROCESSOR

  7. Commercial ISA • CDC6600, IBM 360, DEC VAX (good old days, 360 is now IBM z-series) • x86 (Intel 32, Intel 64, AMD64), Itanium (IA-64) • Sun Sparc • Xscale (PocketPC) • IBM PowerPC (Mac, BlueGene) • ARM, MIPS (embedded, MIPS once was popular in workstations)

  8. ISA defines a set of “architectural registers” to avoid going to memory all the time X86: EAX, EBX, ECX, EDX, ESI, EDI, EBP, ESP MIPS: r0 to r31 and Hi, Lo (or sometimes we use alias to show the software convention when using these registers) Instruction main classes Arithmetic / Logical Data transfer (load or store for different data sizes) Change-of-flow Conditional branches Unconditional branches (e.g. jump, subroutine calls.) Operands Architectural registers Memory addresses Target address for change-of-flow Basic Instruction Format (Assembly code) <instruction mnemonic> <destination operand>, <source op>, <source op>

  9. MIPS Register Aliases

  10. Basic Instruction Format (Assembly code) <instruction mnemonic> <destination operand>, <source op>, <source op> operation MIPS assembly R8 = R6 + R7  add $8, $6, $7 or  add $t0, $a1, $a2 R9 = R9 + 2004  addi $9, $9, 2004 R3 = R4  R5  xor $3, $4, $5 R10 = R8 << R9  sllv $10, $8, $9 R24 = R15 >> 2  sra $24, $15, 2 (arith right shift) R2 = mem[R3+100]  lw $2, 100($3) mem[R3+100] = R2  sw $2, 100($3) if (R2<R3) R4=1 else R4=0  slt $4, $2, $3 Procedural call  jal _func $31=PC+4; go to address pointed label _func (assuming no delay slot)

  11. rd rt add $4, $3, $2 rs 31 26 25 21 20 16 15 11 10 6 5 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 opcode rs rt rd shamt funct 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 MIPS R-format Encoding 31 26 25 21 20 16 15 11 10 6 5 0 opcode rs rt rd shamt funct Encoding = 0x00622020

  12. 31 26 25 21 20 16 15 11 10 6 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 0 opcode rs rt rd shamt funct 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 0 MIPS R-format Encoding 31 26 25 21 20 16 15 11 10 6 5 0 opcode rs rt rd shamt funct rd shamt sll $3, $5, 7 rt Encoding = 0x000519C0

  13. 31 26 25 21 20 16 15 0 1 0 0 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 1 1 0 0 0 opcode rs rt Immediate Value 1 0 0 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 1 1 0 0 0 MIPS I-format Encoding 31 26 25 21 20 16 15 0 opcode rs rt Immediate Value rt Immediate lw $5, 3000($2) rs Encoding = 0x8C450BB8

  14. 31 26 25 21 20 16 15 0 1 0 1 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 1 1 0 0 0 opcode rs rt Immediate Value 1 0 1 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 1 1 0 0 0 MIPS I-format Encoding 31 26 25 21 20 16 15 0 opcode rs rt Immediate Value rt Immediate sw $5, 3000($2) rs Encoding = 0xAC450BB8

  15. X Target Address 31 26 25 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 opcode Target Address 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 MIPS J-format Encoding 31 26 25 0 opcode Target Address Target • jal will jump and push • return address in $ra ($31) • Use “jr $31” to return jal 0x00400030 0000 0000 0100 0000 0000 0000 0011 0000 Instruction=4 bytes Encoding = 0x0C10000C

  16. 31 26 25 21 20 16 15 11 10 6 5 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 1 rd (default=31) opcode rs 0 0 funct 31 26 25 21 20 16 15 11 10 6 5 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 opcode rs 0 0 funct JR and JALR • JALR (Jump And Link Register) and JR (Jump Register) • Considered as R-type • Unconditional jump • JALR used for procedural call jalr r2 jr r2

  17. Assembly Program Example .data .globl array array: .word 0x12345678 .word 0x98765432 .word 0x66bbccdd .word 0x44332211 .text .globl __start __start: jal main # more code below .globl main main: la $8, array lb $9, ($8) lb $10, 1($8) add $11, $9, $10 sb $11, ($8) addiu $8, $8, 4 lh $9, ($8) lhu $10, 2($8) add $11, $9, $10 sh $11, ($8) addiu $8, $8, 4 lw $9, ($8) lw $10, 4($8) sub $11, $9, $10 sw $11, ($8)

  18. Interface for System Services

  19. Backup

  20. CISC Complex Instruction Set Computers versus RISC Reduced Instruction Set Computers ISA Design Philosophy • IBM 801 led by John Cocke pioneered RISC concept • Berkeley’s RISC-I and Stanford’s MIPS led the first academic implementations

  21. RISC versus CISC • Why CISC? • Memory are expensive and slow back then • Cramming more functions into one instruction • Using microcode ROM (μROM) for “complex” operations • Justification for RISC • Complex apps are mostly composed of simple assignments • RAM speed catching up • Compiler (human) getting smarter • Frequency shorter pipe stages (also easier to design a regular pipeline)

  22. Other ISA Design Philosophy • VLIW (Very Long Instruction Word) • A Dumb Machine with a Smart Compiler • Packing multiple (RISC-like) operation into one VLIW • Instruction scheduling performed completely by compiler • Multiflow, Cydrome in the 80s and most of the digital signal processor (DSP) today • EPIC (Explicit Parallel Instruction Computing) • The return of the VLIW • With new features in the ISA such as • Data and control speculation • Full Predication • Intel/HP’s Itanium and Itanium 2 (or once called IA-64)