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MonolithIC 3D ICs

MonolithIC 3D ICs. November 2012. MonolithIC 3D Inc. , Patents Pending. Monolithic 3D RC-JLT (Recessed-Channel Junction-Less Transistor ). Technology.

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MonolithIC 3D ICs

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  1. MonolithIC 3D ICs November 2012 MonolithIC 3D Inc. , Patents Pending MonolithIC 3D Inc. , Patents Pending

  2. Monolithic 3D RC-JLT (Recessed-Channel Junction-Less Transistor) MonolithIC 3D Inc. Patents Pending

  3. Technology • Monolithic 3D IC technology is applied to producing monolithically stacked low leakage Recessed Channel Junction-Less Transistors (RC-JLTs).Junction-less (gated resistor) transistors are very simple to manufacture, and they scale easily to devices below 20nm: •  Bulk Device, not surface •  Fully Depleted channel •  Simple alternative to FinFET • Superior contact resistance is achieved with the heavier doped top layer. The RCAT style transistor structure provides ultra-low leakage.Monolithic 3D IC provides a path to reduce logic, SOC, and memory costs without investing in expensive scaling down. MonolithIC 3D Inc. Patents Pending

  4. RCJLT – a monolithic process flow Using a new wafer, construct dopant regions in top ~100nm and activate at ~1000ºC Oxide N+ ~100nm N++ P- Wafer, ~700µm MonolithIC 3D Inc. , Patents Pending 4

  5. Implant Hydrogen for Ion-Cut H+ Oxide N+ ~100nm N++ P- Wafer, ~700µm MonolithIC 3D Inc. Patents Pending

  6. H+ Hydrogen cleave plane for Ion-Cut formed in donor wafer Oxide N+ ~100nm N++ ~10nm P- Wafer, ~700µm MonolithIC 3D Inc. Patents Pending

  7. H+ Flip over and bond the donor wafer to the base (acceptor) wafer Donor Wafer, ~700µm P- N++ ~100nm N+ Oxide 1µ Top Portion of Base Wafer Base Wafer, ~700µm MonolithIC 3D Inc. Patents Pending

  8. Perform Ion-Cut Cleave N++ ~100nm N+ Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Base Wafer ~700µm 8

  9. Complete Ion-Cut N++ ~100nm N+ Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Base Wafer ~700µm 9

  10. Etch Isolation regions as the first step to define RCAT transistors N++ ~100nm N+ Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Base Wafer ~700µm 10

  11. Fill isolation regions (STI-Shallow Trench Isolation) with Oxide, and CMP N++ ~100nm N+ Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Base Wafer ~700µm 11

  12. Etch RCAT Gate Regions Gate region N++ ~100nm N+ Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Base Wafer ~700µm 12

  13. Form Gate Oxide N++ ~100nm N+ Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Base Wafer ~700µm 13

  14. Form Gate Electrode N++ ~100nm N+ Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Base Wafer ~700µm 14

  15. Add Dielectric and CMP N++ ~100nm N+ Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Base Wafer ~700µm 15

  16. Etch Thru-Layer-Via and RCJLT Transistor Contacts N++ ~100nm N+ Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Base Wafer ~700µm 16

  17. Fill in Copper N++ ~100nm N+ Oxide 1µ Top Portion of Base Wafer MonolithIC 3D Inc. Patents Pending Base Wafer ~700µm 17

  18. Add more layers monolithically N++ ~100nm N+ Oxide N++ ~100nm N+ Oxide 1µ Top Portion of Base (acceptor) Wafer Base Wafer ~700µm 18 MonolithIC 3D Inc. Patents Pending

  19. Benefits for RCJLT • 2x lower power • 2x smaller silicon area • 4x smaller footprint • Layer to layer interconnect density at close to full lithographic resolution and alignment • Performance of single crystal silicon transistors on all layers in the 3D IC • Scalable: scales naturally with equipment capability • Forestalls next gen litho-tool risk • Also useful as Anti-Fuse FPGA programming transistors: programmable • interconnect is 10x-50x smaller & lower power than SRAM FPGA • Base logic circuits could be UT-BBOX, FinFET, or JLT CMOS logic devices MonolithIC 3D Inc. Patents Pending

  20. RC-JLT flow: Summary Create a layer of Recessed Channel Junction-Less Transistors (RC-JLTs), a junction-less version of the RCAT used in DRAMs, by activating dopants at ~1000°C before wafer bonding to the CMOS substrate and cleaving, thereby leaving a very thin doped stack layer from which transistors are completed, utilizing less than 400°C etch and deposition processes. MonolithIC 3D Inc. Patents Pending

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