Midterm Project Report Double buffer SDRAM Memory Controller Project Number: D0713 Presented by: Yael Dresner Andre Steiner Instructed by: Michael Levilov
Project Description • Implementation of a device that receives a grayscale bit map video stream from a digital video camera, performs a simple pixel processing and transfers it to a CPU through a double buffer SDRAM memory.
Blocks Diagram CAMERA CPU FPGA SDRAM controller read part SDRAM controller write part Pixel Processing Unit Sync Switch FIFO Data Bus SDRAM B SDRAM A Control signal
Camera Module • This module is implemented by a test-bench process, which simulates a digital video camera. Pixels Data Test Bench reset 2 us interval between lines Start pulse synch 1024 pixels * t clock period Clock – 100MHz
Pixel Processing Module Pixels Data Processed Pixels Data Simple image processing reset synch synch clock
Write Controller Module Input Data Pixels Data DataPath Addresses Start pulse reset Moore State Machine Control synch clock
Write Controller Module Initialization Write full page Refresh
Write Controller Module Write Algorithm • The data is sent to the Sdram block and switched to the Sdram memory which is not used for reading. The switching is done by a different unit in the read controller. • The data is written to the memory in Full-Page mode (bursts of 1024 bytes). • One bank is used (out of four). • Refresh cycles are being done in the time interval between lines.
Switching Diagram SDRAM controller read part SDRAM controller write part Switch SDRAM B SDRAM A
Write Controller Module Refresh Algorithm • One refresh cycle : 80ns (8 clock periods) • Time interval between 2 lines : 2us • 2us/80ns = 25refresh cycles • In order to refresh all the4096lines we need4096/25 (163.84)time intervals • Refreshing the whole memory takes163.84*(2us + 1024*10ns) = 2msec • Each line should be refreshed every64 msec
Cpu Module • This module is implemented by a test-bench process, which simulates a Cpu. • The Cpu asks for the data pixels randomly, using the “RD” control line. • The Cpu reads bursts of bytes from the fifo, after receiving a “RDY” control line. The burst length is set randomly for each request.
Handling Cpu Request RD RD Read Controller Test Bench SYNCH MODULE RDY RDY read write FIFO Pixels Data Read Part Write Part Cpu Clock -100MHz Sdram Clock
Read Controller Module • Read Controller Responsibilities • Handling The switching between Sdrams • Reading from Sdram and writing to fifo • Refreshing • Handling Cpu requests & reading data from FIFO to Cpu
Read Controller Module Reading from Sdram algorithm • The read controller ensures that the FIFO is always full. • The read controller keeps 2 pointers: • The address from which reading should continue • The address which once accessed, switching should occur. This is the last address of data that was written before the previous switching.
Read Controller Module Refreshing algorithm • The read controller is responsible for the refreshing of the Sdram that is currently switched for reading. • Refreshing all Sdram lines should be done every 64 ms. This process takes 4096*80ns=0.33ms • during this time the data is not transferred to the FIFO.
Read Controller Module Switching algorithm • Switching is done after: • Thelast address of data that was written is read to the FIFO • Time interval between lines and refreshing of the write controller is done • Before switching the write controller stores the last address of written data and sends it to the read controller
Read Controller Module Reading from Sdram Unit Fifo Handling unit Switching Unit Control Control & Address FIFO Switch SDRAM B SDRAM A
Alternative Write Algorithm Full page mode Burst mode 1 bank 4 banks Less complicated implementation of the write & read controllers More complicated implementation of the write & read controllers
Time Schedule • Implementing the camera test-bench module • Implementing the pixel processing unit • Implementing the write part of the SDRAM (Initialization, writing and refreshing) • Implementing the Cpu Test Bench – One week • Implementing the fifo and sync module – One week • Implementing the read controller –Two weeks • Integration and testing – Two weeks • learning synthesys and PLACE&ROUTE" tools – Two weeks • Documentation