Status of the CSC Track-Finder

1. Status of the CSC Track-Finder Darin Acosta University of Florida

2. CSC Sector Processor Prototype 2 15 × 1.6 Gb/soptical link connections from CSC electronics Xilinx Virtex-2 800 User I/O CMS Week

3. Test Status • Basically all functionality has been successfully tested • Optical links: • Demonstrated to work error-free during Sept’03 beam test with home-built PLL+VCXO and with latest QPLL (TTCRq) • LUT Tests: • Validated loading and read-back of all 45 SR LUTs and 3 PT LUTs using random numbers and simulated muon LUT files • SP Track-Finding Logic Tests: • Downloaded random data and simulated muon data into 512 BX input FIFO, read-back and compare output FIFO • No discrepancies in 1.2M random events • No discrepancies in 13K single muon events, or 4K triple muon events (3 single muons piled up) • Verilog model also “installed” into ORCA • Complete functionality test • Input FIFO  LUTs  Track-Finding  output FIFO CMS Week

4. Interface Tests • MPC to Sector Processor • Validated with optical link tests • SP to Muon Sorter Test • Data successfully sent from SP to Muon Sorter and received properly. Read-back of winner bits also correct. • Tested 10/12 slots on custom GTLP backplane • Plan multiple SP to MS test • DT/CSC Data Exchange Test • Demonstrated to work during Sept’03 in both directions, with only a few minor problems with swapped bits, connectors, and dead chips • Clock and Control Board (TTC interface) • New design based on discrete logic and with TTCRq installed still needs to be tested (beginning April) CMS Week

5. Beam Test Goals June structured beam period • Base goal: • Set up pre-production system and repeat prior tests using 25 ns structured beam • New CCB design • Additional goals: • Test TMB2004 with RAT • Use new DDU+DCC (FED) developed by OSU • Use fully functional Track-Finder system (self-triggering) • Use fully functional XDAQ-based event builder and run control • Use new crate controller developed by OSU • Add an ME1/2 chamber in order to have 3-chamber test (for SP) • Swap ME1/1 in for ME1/2 • Mount an endcap RPC on ME1/2, connect Link board to RAT, record RPC data in TMB • Add a small block of iron absorber between (15x15x30 cm?) to validate OSCAR/ORCA simulation CMS Week

6. RPC ALCT Transition board TMB TMB + RAT Preproduction boards • Final prototypes produced and passed all tests. • 27 preproduction TMB-RAT sets being produced, 10 of these delivered and are being tested. CMS Week

7. Rad-Tolerant CCB Prototype • Basic VME interface is implemented using discrete logic • Critical functions of CCB will be immune to SEU • New TTCrq mezzanine with QPLL ASIC • Has an FPGA for flexibility • Status • 7 prototype boards being produced. • 1 board delivered. • Hardware looks good. • Testing and debugging in progress. CMS Week

8. Updates to Track-Finder • Firmware improvements • Multiple-BX input acceptance for track segments • Track-Finding parameters under VME control (e.g.  windows) • Error counters, track segment counters, track counters for monitoring • Ghost-busting at sector boundaries • Increases di-muon trigger acceptance to ||<2.4 when low quality CSC tracks included • Installed into ORCA • Self-trigger capability • A Level-1 Accept signal can be generated based on the presence of a track for beam test use • Goes onto bussed backplane to CCB, then out front-panel • New DT/CSC transition card designed • SCSI connectors on one side of card • Ability to perform self-test with tester card • Fabrication completed by May 2004 • Plan another DT/CSC interface test in Oct’04 CMS Week

9. New DT/CSC Transition Board Layout CMS Week

10. CSC Track-Finding Latency 11  25 ns, or 275 ns CMS Week

11. CSC Trigger Latency • Measured with scope during the beam tests: • From CSC to MPC input: 32 bx ( 1 bx) • From the CSC to SR/SP input: 57 bx(includes 90 m fiber, 18 bx delay) • Estimated latency for output of SP: • Add 11 bx for SR/SP processing: 68 bx • Estimated latency for output of Muon Sorter: • Add 7 bx for backplane + sorting: 75 bx • Total compares well with 74.5 bx projected in TDR • (Latter includes 1 bx TOF delay) • Hope to save additional ~7 bx with “Virtex-2” TMB • Estimated latency to send CSC data to DT TF: • 1bx TOF + 57bx + 5bx for SR + 2bx cable: 65 bx – 7 bx = 58 bx • Nearly aligned with DT data at DT TF: 54 bx according to TDR CMS Week

12. CSC Track-Finder Rack Layout CMS Week

13. CSC Track-Finder Milestones CSC Bckpl Proto tested Sep-02 Delay: Mar-04 DoneCSC CCB Proto tested Sep-02 Done New design tested Jun-04CSC SR/SP Proto tested Mar-03 Delay: Mar-04 ~Done, wait for Jun-04 testCSC MPC Proto tested Mar-03 Delay: Mar-04 ~Done, wait for Jun-04 testCSC SR/SP-MPC-CCB Tested Jun-03 Delay: Mar-04 ~Done, wait for Jun-04 testCSC Sort Proto done Aug-03 DoneCSC Sort Proto Tested Nov-03 Delay: Mar-04 Needs GMT testCSC Sort Final Bd done Mar-04 Delay: Oct-04CSC Bckpl Prod. done Mar-04 Delay: Oct-04CSC CCB Prod. done Mar-04 Delay: Oct-04CSC Sort Final Bd Test Jun-04 Delay: Jan-05CSC SR/SP Prod. done Jun-04 Delay: Oct-04 Delayed to Jan-05CSC MPC Prod. done Jun-04 Delay: Oct-04CSC Bckpl Prod. tested Aug-04 Delay: Jan-05CSC CCB Prod. tested Aug-04 Delay: Jan-05CSC SR/SP Prod. tested Nov-04 Delay: Jan-05 Delayed to Mar-05 CMS Week