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Aravindh Anantaraman * , Kiran Seth † , Eric Rotenberg * , Frank Mueller ‡

Enforcing Safety of Real-Time Schedules on Contemporary Processors using a Virtual Simple Architecture (VISA). Aravindh Anantaraman * , Kiran Seth † , Eric Rotenberg * , Frank Mueller ‡. Center for Embedded Systems Research (CESR) * Electrical & Computer Eng./ ‡ Computer Science

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Aravindh Anantaraman * , Kiran Seth † , Eric Rotenberg * , Frank Mueller ‡

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  1. Enforcing Safety of Real-Time Schedules on Contemporary Processors using a Virtual Simple Architecture (VISA) Aravindh Anantaraman*, Kiran Seth†, Eric Rotenberg*, Frank Mueller‡ Center for Embedded Systems Research (CESR) *Electrical & Computer Eng./ ‡ Computer Science North Carolina State University † Qualcomm. Inc RTSS–25

  2. Complexity in Hard-Real-Time Systems • Worst-case execution time (WCET) crucial for schedulability analysis • Contemporary processors are extremely complex • Branch prediction, pipelining, out-of-order execution • Improve average case performance • WCET unknown • Complex processors not used in real-time systems RTSS–25

  3. Simple Processor Virtual Simple Architecture (VISA) RTSS–25

  4. Simple Processor Virtual Simple Architecture (VISA) Task X WCET = 10 ms RTSS–25

  5. Simple Processor Complex Processor Virtual Simple Architecture (VISA) Task X WCET = 10 ms RTSS–25

  6. Simple Processor Complex Processor Virtual Simple Architecture (VISA) Task X WCET = 10 ms Task X WCET = ?? (unreliable) RTSS–25

  7. Simple Processor Complex Processor Virtual Simple Architecture (VISA) Task X WCET = 10 ms RTSS–25

  8. Simple Processor Complex Processor Virtual Simple Architecture (VISA) Task X WCET = 10 ms Virtual Simple Architecture: give illusion of simple processor RTSS–25

  9. Simple Processor Complex Processor Virtual Simple Architecture (VISA) Task X WCET = 10 ms Task X WCET = 10 ms Virtual Simple Architecture: give illusion of simple processor RTSS–25

  10. Simple Processor Complex Processor Virtual Simple Architecture (VISA) Task X WCET = 10 ms Task X WCET = 10 ms Virtual Simple Architecture: give illusion of simple processor • Novel non-literal approach to static timing analysis • Use simple processor as proxy for complex processor • Dynamically guarantee WCET RTSS–25

  11. Simple Processor Complex Processor Worst-case equivalent systems Virtual Simple Architecture (VISA) Task X WCET = 10 ms Task X WCET = 10 ms Virtual Simple Architecture: give illusion of simple processor RTSS–25

  12. Simple Processor Complex Processor Worst-case equivalent systems 100% 100% processor utilization processor utilization Virtual Simple Architecture (VISA) Task X WCET = 10 ms Task X WCET = 10 ms Virtual Simple Architecture: give illusion of simple processor RTSS–25

  13. Simple Processor Complex Processor Worst-case equivalent systems 100% 100% processor utilization processor utilization worst case worst case Virtual Simple Architecture (VISA) Task X WCET = 10 ms Task X WCET = 10 ms Virtual Simple Architecture: give illusion of simple processor RTSS–25

  14. Simple Processor Complex Processor Worst-case equivalent systems actual exec. time = 8 ms 100% 100% processor utilization processor utilization worst case actual case worst case Virtual Simple Architecture (VISA) Task X WCET = 10 ms Task X WCET = 10 ms Virtual Simple Architecture: give illusion of simple processor RTSS–25

  15. Simple Processor Complex Processor Worst-case equivalent systems actual exec. time = 8 ms 100% 100% dynamic slack processor utilization processor utilization worst case actual case worst case Virtual Simple Architecture (VISA) Task X WCET = 10 ms Task X WCET = 10 ms Virtual Simple Architecture: give illusion of simple processor RTSS–25

  16. Simple Processor Complex Processor Worst-case equivalent systems actual exec. time = 8 ms actual exec. time = 3 ms 100% 100% dynamic slack processor utilization processor utilization worst case actual case actual case worst case Virtual Simple Architecture (VISA) Task X WCET = 10 ms Task X WCET = 10 ms Virtual Simple Architecture: give illusion of simple processor RTSS–25

  17. Simple Processor Complex Processor Worst-case equivalent systems actual exec. time = 8 ms actual exec. time = 3 ms 100% 100% dynamic slack dynamic slack processor utilization processor utilization worst case actual case actual case worst case Virtual Simple Architecture (VISA) Task X WCET = 10 ms Task X WCET = 10 ms Virtual Simple Architecture: give illusion of simple processor RTSS–25

  18. Simple Processor Complex Processor Worst-case equivalent systems actual exec. time = 8 ms actual exec. time = 3 ms 100% 100% dynamic slack dynamic slack processor utilization processor utilization worst case actual case actual case worst case Virtual Simple Architecture (VISA) Task X WCET = 10 ms Task X WCET = 10 ms Virtual Simple Architecture: give illusion of simple processor Exploit dynamic slack for power/energy savings, other functionality RTSS–25

  19. Previous Approaches • Avoid complexity • VISA allows complex processors to be used • Disable complexity during hard-real-time tasks • VISA disables complexity only when problematic • Continue research in timing analysis • WCET of simple proxy improved RTSS–25

  20. VISA Overview • Provides real-time guarantees for contemporary processors • Approach • Execute tasks optimistically on complex mode • Gauge interim progress • Safe back-up mode for anomalous scenarios RTSS–25

  21. Dynamic branch predictor • Complex mode • dynamic branch prediction • superscalar • out-of-order execution • Simple mode • static branch prediction • scalar • in-order execution • Complex mode • dynamic branch prediction • superscalar • out-of-order execution • Simple mode • static branch prediction • scalar • in-order execution Dual-Mode VISA Processor Static prediction RTSS–25

  22. Dynamic branch predictor • Complex mode • dynamic branch prediction • superscalar • out-of-order execution • Simple mode • static branch prediction • scalar • in-order execution • Complex mode • dynamic branch prediction • superscalar • out-of-order execution • Simple mode • static branch prediction • scalar • in-order execution Dual-Mode VISA Processor Static prediction RTSS–25

  23. Dynamic branch predictor • Complex mode • dynamic branch prediction • superscalar • out-of-order execution • Simple mode • static branch prediction • scalar • in-order execution • Complex mode • dynamic branch prediction • superscalar • out-of-order execution • Simple mode • static branch prediction • scalar • in-order execution Dual-Mode VISA Processor Static prediction RTSS–25

  24. Dynamic branch predictor • Complex mode • dynamic branch prediction • superscalar • out-of-order execution • Simple mode • static branch prediction • scalar • in-order execution • Complex mode • dynamic branch prediction • superscalar • out-of-order execution • Simple mode • static branch prediction • scalar • in-order execution Dual-Mode VISA Processor Static prediction RTSS–25

  25. Dynamic branch predictor • Complex mode • dynamic branch prediction • superscalar • out-of-order execution • Simple mode • static branch prediction • scalar • in-order execution Dual-Mode VISA Processor Static prediction RTSS–25

  26. VISA in Action simple mode RTSS–25

  27. VISA in Action simple mode complex mode RTSS–25

  28. VISA in Action simple mode complex mode WCEC Non-speculative simple mode RTSS–25

  29. VISA in Action simple mode complex mode WCEC 1 Non-speculative simple mode RTSS–25

  30. VISA in Action simple mode complex mode WCEC 1 Non-speculative simple mode 2 RTSS–25

  31. VISA in Action simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 RTSS–25

  32. VISA in Action simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 RTSS–25

  33. VISA in Action simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 WCEC’ Successful speculation in complex mode RTSS–25

  34. VISA in Action simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk2 chk3 chk4 WCEC’ chk1 Successful speculation in complex mode RTSS–25

  35. VISA in Action simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk2 chk3 chk4 WCEC’ chk1 Successful speculation in complex mode headstart RTSS–25

  36. VISA in Action simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk2 chk3 chk4 WCEC’ chk1 1 1 Successful speculation in complex mode RTSS–25

  37. VISA in Action simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk2 chk3 chk4 WCEC’ chk1 1 1 Successful speculation in complex mode 2 RTSS–25

  38. VISA in Action simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk2 chk3 chk4 WCEC’ chk1 1 1 Successful speculation in complex mode 2 3 RTSS–25

  39. VISA in Action simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk2 chk3 chk4 WCEC’ chk1 1 1 Successful speculation in complex mode 2 3 4 RTSS–25

  40. VISA in Action simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk2 chk3 chk4 WCEC’ chk1 1 1 Successful speculation in complex mode 2 3 4 $$$ cash back! dynamic slack RTSS–25

  41. VISA in Action simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 WCEC’ Misspeculation in complex mode RTSS–25

  42. VISA in Action simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 WCEC’ chk1 1 1 Misspeculation in complex mode RTSS–25

  43. VISA in Action simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk2 WCEC’ chk1 1 1 (2) Misspeculation in complex mode RTSS–25

  44. VISA in Action simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk2 WCEC’ chk1 1 1 (2) 2 Misspeculation in complex mode RTSS–25

  45. VISA in Action simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk2 WCEC’ chk1 1 1 (2) 2 Misspeculation in complex mode 3 RTSS–25

  46. VISA in Action simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk2 WCEC’ chk1 1 1 (2) 2 Misspeculation in complex mode 3 4 RTSS–25

  47. WCET preserved in spite of missed checkpoint VISA in Action simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk2 WCEC’ chk1 1 1 (2) 2 Misspeculation in complex mode 3 4 RTSS–25

  48. Contributions • Minimize headstart overhead • Novel zero-overhead VISA approach – dynamic headstart accrual • Extend VISA to multi-tasking systems • Energy evaluation in multi-tasking systems RTSS–25

  49. Headstart Assessment simple mode complex mode RTSS–25

  50. chk1 chk2 chk3 chk4 PEC1 WCEC1 WCEC2 WCEC3 WCEC4 headstart1 Headstart Assessment simple mode complex mode RTSS–25

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