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Hall D Trigger and Data Rates

Hall D Trigger and Data Rates. Elliott Wolin Hall D Electronics Review Jefferson Lab 23-Jul-2003. Outline . Rates from Design Report Comparison with LHC,CLAS… Additional Considerations DAQ Challenges. 1. Rates from Design Report. High trigger rate – 200 KHz

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Hall D Trigger and Data Rates

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  1. Hall D Trigger and Data Rates Elliott Wolin Hall D Electronics Review Jefferson Lab 23-Jul-2003

  2. Outline • Rates from Design Report • Comparison with LHC,CLAS… • Additional Considerations • DAQ Challenges

  3. 1. Rates from Design Report • High trigger rate – 200 KHz • Deadtimeless, pipelined front ends • Small event size – 5 KB • Small Level 1 rejection rate – factor of 2 • Modest rate off detector – 1 GB/sec • Modest Level 3 rejection – factor of 10 • Modest cpu needed in Level 3 – 0.1 SPECint • High rate to tape – 100 MB/sec

  4. 1. Rates, con’t

  5. 2. Comparison with LHC, CLAS… • Compared to LHC, Hall D has: • Similar (LHCb, BTev) or higher trigger rate • Much smaller events • Much smaller rate off detector • Much smaller total trigger rejection • Similar rate to tape • Less cpu/evt needed in Level 3

  6. 2. Comparison with LHC, CLAS… • Compared to CLAS, Hall D has: • Much higher trigger rate • 200 KHz vs 3 KHz • Same size events • Approximately the same number channels • Much higher rate off detector • 1 GB/s vs 25 MB/s • Factor 10 Level 3 rejection • CLAS has no Level 3 • Factor 4 higher rate to tape • 100 MB/s vs 25 MB/s

  7. Hall D KTev KTeV CLAS

  8. Atlas BTev Hall D CMS KTev, CDF, DO, BaBar, CLAS

  9. 3. Additional Considerations • Can not interrupt ROC every event (200 KHz) • Event blocking in front end cpu’s • Timing and trigger distribution • Note that CLAS has: • 25 crates • 1 Trigger supervisor • 1 Event Builder and 1 Event Recorder • No Level 3 farm

  10. Hall D DAQ Baseline Architecture 50-100 front-end crates Gigabit switch 200 KHz 8 event builders 4 Gigabit switches 200 Level 3 Filter Nodes 4 event recorders Network connection to silo 20 KHz 4 tape drives

  11. 3. Additional Considerations, con’t • Crates vs networked front end boards? • If crates used, VME vs CPCI vs ? • (RT)Linux vs VXWorks in front end cpu’s? • Need low-latency interrupt in front end cpu’s? • Location of electronics, crates? • Grounding design?

  12. 4. DAQ Challenges • All problems solved somewhere, many in CLAS • But new to JLab/CODA: • Timing distribution • Event blocking • Many more front end crates • Multiple event builders/recorders • Large Level 3 farm • Multiple, simultaneous DAQ systems (for commissioning) • Need for fault tolerance • Integration with control system • How are we going to do it? • See next talk…

  13. Backup slides

  14. 3. Comparison, con’t

  15. 3. Comparison, con’t

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