1 / 12

A Signature Match Processor Architecture for Network Intrusion Detection

A Signature Match Processor Architecture for Network Intrusion Detection. Authors : Janardhan Singaraju,Long Bu and John A. Chandy, Publisher : IEEE Symposium on Field-Programmable Custom Computing Machines Present: Kia-Tso Chang Date: December 13 2007. 1. outline.

calba
Télécharger la présentation

A Signature Match Processor Architecture for Network Intrusion Detection

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. A Signature Match Processor Architecture for Network Intrusion Detection Authors: Janardhan Singaraju,Long Bu and John A. Chandy, Publisher: IEEE Symposium on Field-Programmable Custom Computing Machines Present: Kia-Tso Chang Date: December 13 2007 1

  2. outline • Signature Match Processor • Character Match Array • Signature Match Array • Address Output Logic • Performance Analysis • FPGA implementation

  3. Signature Match Processor Architecture

  4. Character Match Array

  5. Signature Match Array 5

  6. pseudo-VHDL (p = 4)

  7. SMP Example

  8. Addition of a Cache

  9. match address outputlogic ( MAO logic)

  10. Performance Analysis • the time to process a b byte packet is b/p+M+1 cycles where M is the number of matches found in the packet. b/p corresponds to the time for the packet to stream through the SMP signature matches and M + 1 is the time to do the matched address output.

  11. SMP Resource Utilization

  12. Comparison NIDS FPGA Designs

More Related