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WAPP – 2011, Bose Institute, Darjeelig 18 th December, 2011

Electronics R&D Projects @ GRAPES -3 in collaboration with VIIT Pune Atul Jain On Behalf of GRAPES-3 Collaboration. WAPP – 2011, Bose Institute, Darjeelig 18 th December, 2011. FPGA based 8 Ch. Scalar (2010-2011). Input Translator. FPGA. USB Interface. PC. Implementation.

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WAPP – 2011, Bose Institute, Darjeelig 18 th December, 2011

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  1. Electronics R&D Projects@GRAPES -3in collaboration with VIIT PuneAtul JainOn Behalf of GRAPES-3 Collaboration WAPP – 2011, Bose Institute, Darjeelig 18th December, 2011

  2. FPGA based 8 Ch. Scalar (2010-2011) Input Translator FPGA USB Interface PC

  3. Implementation • Development boards for Atmel FPGA • PCB for Input Level Translator and microcontroller mounting. • GUI for Windows

  4. Real World Test

  5. 12th JULY 2011

  6. Projects for 2011-2012 • Software • Web interface for ROOT Monitoring • Root Program Development • Data Base Management for all • activities at GRAPES -3 • GRAPES-3 Web page hosting at • Ooty with active link to all • Monitoring and DBMS • Hardware • 32 Ch. SCALAR with USB interface • 64 Ch. SCALAR with Trigger Logic and TCP/IP interface • High Voltage and Current Monitoring and Recording using USB intreface • Voltage & Temperature monitoring along with Voltage control for SiPM

  7. 1 . FPGA based 32 Ch. Scalar Input Translator FPGA USB Interface PC

  8. 32 Ch Scalar PCB

  9. In House Soldering

  10. Status • Board under test at VIIT • GUI development for Linux • Early January ready for test bench demonstration

  11. 2 . FPGA based 64 Ch. Scalar and Trigger module with TCP/IP Protocol Input Translator FPGA TCP/IP Interface PC

  12. BLOCK DIAGRAM

  13. OPTO – ISOLATOR AND LEVEL CONVERSION • Opto-Isolation and Level Conversion • Conversion from TTL to LVTTL • Discriminator: TTL (5V) • FPGA: LVTTL (3.3V) • Opto-Isolation: To get a clean digital pulse

  14. Memory Management SPARTAN6 LX9 FPGA Counter , Trigger Logic • SPARTAN6-LX9 FPGA • For counting the input pulses of 64 channels • Defining a block of memory to store the count and its management • FEATURES: • 60 to 160MHz Reference Clock support • TQG144 package with 102 user I/Os • 9,152 logic cells and 11,440 Flip-Flops

  15. LPC2478 Micro-controller • On-chip Ethernet, USB , UART, CAN, SPI support • ARM7TDMI-S processor, running at up to 72 MHz • 512 kB on-chip flash program memory with ISP and IAP • 98 kB on-chip SRAM • LQFP208 package with 160 GPIO pins LPC2478 ARM7 Core based Micro-controller CAN USB RS232 RS485 SRAM

  16. Ethernet Transceiver: DP83848 • Temp Range: -40 to 85 C • Single Port 10/100 Mb/s • MII support • An embedded web-server can be implemented and stored in the flash memory which will facilitate the user to access the information about each board through any web-browser • Data-Logging • GUI in LINUX FLASH MEMORY ETHERNET TRANSCEIVER PC GUI

  17. Future Long term Applications • Scheme would be adopted for • Designing compact and portable test benches • Enhancing the monitoring of parameters • Large DAQ to be installed at GRAPES-3 ( 4000 nos of Proportional Counters)

  18. THANKS

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