Controlling the System

1. Controlling the System This material exempt per Department of Commerce license exception TSU

2. Objectives • Describe the control mechanism available in System Generator • State the available blocks in System Generator to control data movement • Describe how to design state machines • Distinguish between valid and invalid data After completing this module, you will be able to:

3. Outline • Control Mechanisms • Clock Enables and Reset • Valid and Invalid Data • Control Blocks • MicroBlaze (FSL) • M-Code Block • Expression Block • PicoBlaze • PowerPC/MicroBlaze (App Note) • Simulink Tips and Tricks • Masked Subsystems • Icon Editor • Parameter Initialization • Documentation Editor • Lab 5: Controlling the System

4. Control MechanismsEnable and Reset Ports • Many blocks have optional Enable ports • Gated by the CE signal going to the block • When the CE signal is de-asserted the block holds its current state until the enable signal is asserted again or the reset signal is asserted • The enable signal has to run at a multiple of the block's sample rate • The signal driving the enable port must be Boolean • Some blocks have an optional Reset port • Gated by the CE signal going to the block • Reset port has precedence over Enable port when both are present • When the reset signal is asserted the block goes back to its initial state • The reset signal has to run at a multiple of the block's sample rate • The signal driving the reset port must be Boolean

5. Control Mechanisms Clock Enable Port • SysGen infers the clock from the design sample times, and abstracts away the Clock Enables • In multi-rate systems further Clock Enables are inferred due to the more complex hardware elaboration scheme. This is covered in next module • This clock enables are ANDed with optional enable ports, which users can turned-ON from the block parameters

6. System Clock DIN 0 7 2 1 4 7 8 11 3 0 6 3 1 2 CE 5 0 0 1 DOUT 1 8 Clock Enable Behavior • CE is modeled to reflect the hardware behavior • Output changes one clock cycle after CE is asserted

7. Control Pin Cheat Sheet ?? – Depending on application corresponding pin(s) may exist

8. Control Pin Cheat Sheet

9. Control Mechanism Valid and Invalid Ports • Issue: How to model ‘invalid data’ in the confines of a System Level environment. Required for data burst applications, one-shot FFTs, and latency output from high level cores • Solution:Certain blocks have a ‘valid bit’ input (vin) that is a control signal to the data input. It is also accompanied by a valid out (vout) signal that signals whether the output data is valid • Most high level blocks have ‘valid’ input and output ports

10. Valid Bits • There are several conditions that result in a Xilinx block producing indeterminate data, which is represented as ‘not a number’ or NaN in Simulink • One case is with the Dual-Port Memory block, when there is a write-write collision on a particular address. Consequently, in Simulink simulation, the corresponding data is marked as indeterminate • A block having vin and vout ports may produce indeterminate values, for example to model pipeline flushing at the beginning of a simulation, but will have accompanying vout set to 0 • Special attention should be paid if you encounter indeterminate data in a model, because it indicates unobservable behavior in the ultimate hardware • System Generator will catch some instances of indeterminate data as simulation errors in Simulink, when this represents a semantic problem with your model • Be aware that although these design errors will be caught in Simulink simulation, such cases will not be detected in hardware

11. Valid Bits • Blocks that have Valid bit modeling: • FIR (optional) • FFT • Reed Solomon Encoder/Decoder • Viterbi Decoder • Convolutional Encoder • Interleaver/DeInterleaver • CIC

12. Valid Bits Question • Cost in hardware • The SysGen block typically has a ‘valid bit’ pipe parallel to the data path. The length of the pipe is equal to the latency of the block • An AND gate controls the data path input What would be the most efficient way of implementing the valid pipe?

13. Outline • Control Mechanisms • Clock Enables and Reset • Valid and Invalid Data • Control Blocks • EDK Processor • M-Code Block • Expression Block • PicoBlaze • PowerPC/MicroBlaze (App Note) • Simulink Tips and Tricks • Masked Subsystems • Icon Editor • Parameter Initialization • Documentation Editor • Lab 5: Controlling the System

14. Modeling Control Circuits • System Generator provides many ways to model Control Circuits • Develop DSP peripherals for MicroBlaze (via FSL) • M-Code block for subset of MATLAB m-code compilation • Gives designer more design language choice • Expression block for bit-wise logical operations • Provides simple level control using Logical and Boolean expressions • Xilinx PicoBlaze 8-bit soft microprocessor block • Allows designers to model more complex control functions • Develop DSP Peripherals for 32-bit PowerPC/MicroBlaze (app note)

15. FPGA Custom Peripherals • Interfacing a SysGen design to a processor • Co-processor (custom peripheral) off-loads computation from processor • Processor off-loads control from peripheral • Processor may be embedded or an external device • Embedded processors • PowerPC 405 (V-II Pro / V-4 FX) • MicroBlaze (all Virtex / Spartan families) • DSP & General Purpose processors (GPPs) • TI DSP processor • Intel Pentium device (e.g., video or graphics co-processor)

16. Synthesized interface DSP Co-Processor RAM RAM FIFOinterface mP In BusAdaptor FIFO FIFO Out Reg Reg Virtual links between shared memories Interfacing to Processor • Processor / EDK Interfaces • The HW / SW interface • Bus agnostic methodology • Design peripherals that communicate through memories • User associates memory blocks to a processor • Tool synthesizes memory-to-bus interface • Bus adaptor: FIFO, EMIF, CoreConnect,…

17. Seamless EDK integration • Hardware co-simulation • supported like other Sysgen block: you can have a MB and other sysgen blocks in cosim • import almost any arbitrary EDK system (single processor, MB only) • Shared-memory based interface into processor • Automatic software driver generation • Automatic documentation generation

18. Configure processor for EDK export mode Memories visible to processor visible in tree view Right clicking on tree view reveals more options Clicking OK will cause memory map to be generated. You can force a regeneration by selecting “Sync Memories” EDK Processor Block

19. Automatically- generated memory map documentation. Each shared memory accessible from software is listed here. Identifier names used as arguments in software driver calls. In Sysgen diagram there will be a shared FIFO called “sg2mb_fifo”. Hyperlinks to example code showing how to read/write memory. Memory Map Documentation

20. Software Drivers The generated software drivers contain six basic functions for accessing shared-memories • int <inst>_Read (unsigned int memName, unsigned int addr, unsigned int* val); • int <inst>_ArrayRead (unsigned int memName, unsigned int startAddr, unsigned int transferLength, unsigned int** valBuf); • int <inst>_Write (unsigned int memName, unsigned int addr, unsigned int val); • int <inst>_ArrayWrite (unsigned int memName, unsigned int startAddr, unsigned int transferLength, const unsigned int* valBuf); • unsigned int <inst>_GetFifoDataCount (unsigned int memName); • unsigned int <inst>_GetFifoEmptyCount (unsigned int memName);

21. MCode Block GUI

22. MCode Block Examples • MCode block enhancements • Vector state variables • Addressable shift register function q = asr(din, addr, en, depth) persistent regs, regs = xl_state(zeros(1, lat), din, depth); q = regs(addr); if en regs.push_front_pop_back(din); end • For loops • Bit reversal function q = bitreverse(d) q = xl_slice(d, 0, 0); for i = 1:xl_nbits(d)-1 q = xl_concat(q, xl_slice(d, i, i)); end

23. Expression Block • Performs a bitwise logical expression • The expression is specified with operators • And - & -- highest precedence • Or - | • Not - ~ • Xor - ^ -- lowest precedence • Precedence can be changed using parenthesis • The number of input ports is inferred from the expression • Maximum of 16 possible input ports • The input port labels are identified from the expression, and the block is subsequently labeled accordingly • Block Parameters • Expression : Bitwise logical expression • Align Binary Point : specifies that the block must align binary points automatically. If not selected, all inputs must have the same binary point position

24. Expression Block • Entering following expression in the block parameters Expression field will generate the resulting symbol • ~((A1 | A2) & (B1 ^ B2))

25. 8-bit PicoBlaze Controllerwithin Simulink • PicoBlaze provides8-bit microprocessortype control • Xilinx’s Home-Grown 8-bit processor • Very compact (85 slices) • 49 instructions • Assembly language • 2 clocks/instruction • 10,000+ users For more information on the Picoblaze microprocessor, visit:http://www.xilinx.com/ipcenter/processor_central/picoblaze/index.htm

26. Host PC (post-processing and filter design in Matlab) PowerPC/MicroBlaze Use System Generator to Develop DSP Peripherals for OPB Application Note XAPP264 Using SysGen to Create CoreConnectTM Peripherals • XAPP264 shows designers how to use Simulink & System Generator to create DSP peripherals that can connect to the OPB • PowerPC • MicroBlaze • This enables 32-bit control for XtremeDSP using: • VirtexTM-II, Virtex-II ProTM • Spartan-3 • Still need EDK to program the processor UART Lite Reloadable DA FIR Peripheral OPB

27. Outline • Control Mechanisms • Clock Enables and Reset • Valid and Invalid Data • Control Blocks • MicroBlaze (FSL) • M-Code Block • Expression Block • PicoBlaze • PowerPC/MicroBlaze (App Note) • Simulink Tips and Tricks • Masked Subsystems • Icon Editor • Parameter Initialization • Documentation Editor • Lab 5: Controlling the System

28. Masked Subsystems • Simulink provides the power to “personalize” a subsystem. This is called masking • This enables you to: • Generate custom macro blocks with a custom icon • Create a parameter dialog box for the block • Create your help for the block • Shield complexity of the internals of the block • Protect the contents of a block from ‘dirty hands’

29. Masking a Subsystem • Right click on a subsystem and select “Mask Subsystem” (Ctrl+M) • The Mask editor contains the: • Icon editor • Parameters editor • Initialization editor • Documentation editor • To disable a mask simply click unmask on the mask editor

30. Icon Editor • The Icon tab controls the appearance of the icon • The drawing commands edit box allows the use of MATLAB syntax plotting and image commands to define your icon. Try: • plot(peaks) • disp(‘my Icon’) • image(imread(‘xilinx.jpg’)) • Play with the other properties to view their effects

31. Parameters Editor • The Parameters tab enables you to define and describe mask dialog box parameter prompts and name the variables associated with the parameters • Users must: • Add a parameter • Give a prompt name • Assign a variable name to pass the value to • Select the type of variable • Select if enabled or not • Select if tunable or not

32. Initialization Editor • Initialization tab allows you to specify initialization command • After this, MATLAB workspace variables are no longer visible • Simulink executes the initialization commands when it • Loads the model • Starts the simulation • Updates the block diagram • Rotates the masked block • Redraws the block's icon (if the mask's icon creation code depends on variables defined in the initialization code)

33. Documentation Editor • There are three fields: • Mask type • Mask description • Mask Help (can be written in html). Click Help in the block mask to access the block help Type ‘maskedsubsytem’ to view the example

34. Outline • Control Mechanisms • Clock Enables and Reset • Valid and Invalid Data • Control Blocks • MicroBlaze (FSL) • M-Code Block • Expression Block • PicoBlaze • PowerPC/MicroBlaze (App Note) • Simulink Tips and Tricks • Masked Subsystems • Icon Editor • Parameter Initialization • Documentation Editor • Lab 5: Controlling the System

35. Lab 5:Controlling the System • In this lab, you are to create an address generator to control the storage of samples and coefficients for a 92 tap MAC-based FIR filter, using • Xilinx Blockset’s predefined blocks • Xilinx Blockset’s MCode block • Below is a block diagram of the MAC-based FIR filter Sample Memory Accumulator Full Multiplier • Cyclic RAM buffer Capture of final result 8 Sample 27 27 in Samples CE + 20 92 × 8 D Q D Q Sample + Address 12 Coefficients Coefficient 92 × 12 Address

36. N-1 yn = S xn-i hi i=0 Lab 5:Controlling the System • One way to implement this filter is to store the filter coefficients and samples in a dual port block RAM used as a cyclic RAM buffer • The dual port RAM will be used in a mixed mode configuration with the data written and read from port A (RAM mode) and the coefficients read from port B (ROM mode) • Your task is to generate the logic that will drive each address port of the Dual Port Block Memory • y(0) = h(0) x(0) • y(1) = h(1) x(0) + h(0) x(1) • y(2) = h(2) x(0) + h(1) x(1) + h(0) x(2) • y(3) = h(3) x(0) + h(2) x(1) + h(1) x(2) + h(0) x(3) • etc.

37. x(0) x(3) x(2) x(1) start start Stall one clock cycle at this address Lab 5:Controlling the System The idea is as follows: Read address Fast rate Data buffer x(91) x(90) ... ... Write address Slow rate Read Address sequence: 92 93 94 95 … 183 Read address Fast rate Coefficient array h(0) h(1) h(2) ... ... h(89) h(90) h(91)

38. 0 DIN_A A CE WE_B ADDR_A CYCLIC N-1 COUNTER 0 – N-1 N LOGIC DIN_B ROM B WE_B CYCLIC COUNTER 2N-1 ADDR_B N – 2N-1 RAM MUST BE: READ AFTER WRITE WE WE WE DIN D X X X …X D X X X X … X D X X X X X 1 2 3 ADDR_ A 0 1 2 3 …91 91 0 1 2 3 …90 90 91 0 1 2 3 92 93 94 95 … 183 92 93 94 95 96 …183 92 93 94 95 96 97 ADDR_ B