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Another 3U unit to be attached to top of here yet!

Another 3U unit to be attached to top of here yet! (3U unit provides a few more LED’s and the IO to the FPGA board. It will also provide space for an additional FPGA board - Phase 3). All BNCs/Optical Outputs now wired (Note: not yet tested!) ‘D’ Connectors yet to be wired. BACK. FPGA. DC2.

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Another 3U unit to be attached to top of here yet!

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  1. Another 3U unit to be attached to top of here yet! (3U unit provides a few more LED’s and the IO to the FPGA board. It will also provide space for an additional FPGA board - Phase 3)

  2. All BNCs/Optical Outputs now wired (Note: not yet tested!) ‘D’ Connectors yet to be wired

  3. BACK FPGA DC2 DC1 FRONT

  4. Independent Board Tests • DC1 – digital functionality tested and good but SPI/Analogue functionality not tested (This requires the complete system to test) • DC2 – All digital IO tested and appears good. (Static DC testing) • System • All boards as shown in photos power up OK but no firmware yet tested. Wiring to LED’s, BNC’s etc not yet tested. ‘D’ connectors are still to be wired. Third 3U unit to be added – minimal IO on this. • Awaiting an answer on the current requirement for Relays on BPS – it could be a couple of weeks before I have an answer as M. Arnold on A/L. • When I’ve completed the wiring I need to create a map between the VHDL and the physical HW. I will then be in a position to try and download the target control firmware to the FPGA. Hopefully this will be sometime next week, which will permit some initial basic testing of the HW to be done. (No target actuations yet though!) • I will then need to code some additional firmware to permit methodical and thorough testing of the daughter boards functionality. • SW updates to GUI. I will need to liaise with Matt on this but from discussions no problems are foreseen.

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