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Technion - Israel institute of technology department of Electrical Engineering

Technion - Israel institute of technology department of Electrical Engineering . 40Gbit Signal Generator for Ethernet Annual Project. Part A - Final presentation & Part B – Midterm presentation. Mentor : Dr. Bar-On David Developers : Atila Fuad and Ben-Elazar Doron . May 24, 2011.

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Technion - Israel institute of technology department of Electrical Engineering

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  1. Technion - Israel institute of technology department of Electrical Engineering 40Gbit Signal Generator for EthernetAnnual Project Part A - Final presentation & Part B – Midterm presentation Mentor : Dr. Bar-On David Developers : Atila Fuad and Ben-Elazar Doron May 24, 2011 High speed digital systems laboratory

  2. 40Gbit SGAgenda • Project Overview –Reminder • Frame structure • Part A Summary • Part B – Block Diagram • Next Steps • Risks • Gantt Chart

  3. 40Gbit SGBackground - Reminder • Debugging a modern communication chip requires the ability to generate high sped L1 & L2 Ethernet signals on all ports of the chip. • High speed Ethernet signals (41.25 GHz) can be generated by commercial tools, e.g. IXIA, however they are expensive and deal mainly with higher software layers.

  4. 40Gbit SGProject Objectives - Reminder • The Target is to generate 40Gbps Ethernet channel • Split into two semesters: • Project A – Winter Sem. 2010/11: • 10Gbps Traffic. • generate hard coded patterns. • Project B – Spring Sem. 2011: • Continuation of Project A. • Generating 40Gbps Traffic. • GUI Software for Frame Stream Definition.

  5. 40Gbit SGEthernet MAC Frame StructureIEEE 802.3 64 – 1518 Bytes • Preamble – Exists due to historical reasons , contains the constant pattern 0x55 [optional]. • SFD - Marks the start of the frame, and must contain the value 0xD5. • Destination Address - The LSB determines if the address is an individual/ unicast (0) or group/multicast (1) address. • It’s the first field that must always be provided.

  6. 40Gbit SGEthernet MAC Frame StructureIEEE 802.3 64 – 1518 Bytes • Source Address – Must always be provided by the client because it’s not modified by the Ethernet MAC. • Length/Type – If the decimal value of this field is 1536 or greater it’s interpreted as a Type field (Indicates if it’s a VLAN frame or PAUSE/MAC ctrl frame). Otherwise it’s interpreted as a Length field and represents the number of bytes in the following Data field.

  7. 40Gbit SGEthernet MAC Frame StructureIEEE 802.3 64 – 1518 Bytes • Data – Varies from 0-1500 Bytes, must always be provided. • Pad – Used to ensure that the frame length is at least 64 bytes in length, and required for successful CSMA/CD operation. • CRC-32-Calculated over the destination address,source address, length/type, data, and pad fields using a 32-bit Cyclic Redundancy Check (CRC). If an incorrect FCS value is received it indicates that the received frame is bad.

  8. 40Gbit SGPart A Requirements • Transmit Ethernet MAC frame according to IEEE 802.3 standard using FPGA • Establish 10Gbps link between Stratix-IV board and IXIA link-partner. • Establish a link using SFP+ module connected by fiber cable to LP. • Receive by IXIA valid frames that were transmitted by Stratix-IV board. • Programming design blocks using the coming software tools: • Quartus 10.2 Design Tool • Altera USB Programming Tool • The Mega Core Functions • AlteraSignalTaptool • Hardware Programming Language: VERILOG & VHDL

  9. 40Gbit SGPart A System HardwareComponents • The Stratix IV GT HTG-S4Gx-PCIE Board with 10Gbps SFP+ modules • Link Partner – IXIA • PC with the above software tools (for design programming). • SFP+ Modules • Altera USB Programming Cable • Fiber Optic Cable

  10. 40Gbit SGPart A Block Diagram MDIO Conf FRAME Gen & Control Module Clock and PLLs ALTGX

  11. 40Gbit SGPart A Proof Of Concept

  12. 40Gbit SGPart A Proof Of Concept

  13. 40Gbit SGPart A Proof Of Concept

  14. 40Gbit SGSystem Block Diagram Final 40Gps Signal Generator

  15. 40Gbit SG Part BFPGA & System Block Diagram IFG Type/Length CRC Source Address Destination Address Part A with AEL2005 Part A with AEL2006 Part A with AEL2006 Part A with AEL2005 Frame Data 40G QSFP Optical Module Frame Data CLOCK System Controller FSM

  16. 40Gbit SGGUI – High Level • To transmit deferent frames patterns • To transmit error frames for validation • Friendly GUI and simple for users • Simple to develop for future developers • Requests flexible and RTL design

  17. 40Gbit SGNext Steps • Activating and Transmitting using both SFP+ Modules whichare connected to the AEL2005 Chips on board the FMC Module. • Activating and Transmitting using both SFP+ Modules which are connected to the AEL2006 Chips on S4G-PCIE board. • Transmitting valid frames in parallel by the 4 SFP+ Modules in 10G link. • Learning about 40 Gigabit Ethernet architecture and standards . • Planning 40G module using 4 modules (10G) of project A . • Planning the 40Gbit Frame Generator module according to Part A . • Get 40Gbit link using all four SFP+ Module. • Transmitting valid frame on 40G link .

  18. 40Gbit SGRisks • Have one board • No link partner for 40G yet • Different PHYs (AEL2005 vs AEL2006) • Lack of technical support to a development board

  19. Gant Chart 40Gbit SGGant Chart

  20. 40Gbit SG Questions ? Thank you …

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