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Technion - Israel institute of technology department of Electrical Engineering

Technion - Israel institute of technology department of Electrical Engineering. 40Gbit Signal Generator for Ethernet Annual Project. Midterm presentation. Developers : Ben-Elazar Doron and Atila Fuad Mentor : Dr. Bar-On David. Dec 30, 2010. High speed digital systems laboratory.

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Technion - Israel institute of technology department of Electrical Engineering

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  1. Technion - Israel institute of technology department of Electrical Engineering 40Gbit Signal Generator for EthernetAnnual Project Midterm presentation Developers : Ben-Elazar Doron and Atila Fuad Mentor : Dr. Bar-On David Dec 30, 2010 High speed digital systems laboratory

  2. 40Gbit SGAgenda • Project Overview –Reminder • Frame structure • FPGA Modules Design • Mini Project- Binary Counter • Gantt Chart

  3. 40Gbit SGProject Objectives - Reminder • The Target is to generate 40Gbps Ethernet channel • Split into two semesters: • Project A – Winter Sem. 2010/11: • 10Gbps Traffic. • generate hard coded patterns. • Project B – Spring Sem. 2011: • Continuation of Project A. • Generating 40Gbps Traffic. • GUI Software for Frame Stream Definition.

  4. 40Gbit SGSystem Block Diagram Reminder

  5. 40Gbit SGEthernet MAC Frame StructureIEEE 802.3 64 – 1518 Bytes • Preamble – Exists due to historical reasons , contains the constant pattern 0x55 [optional]. • SFD - Marks the start of the frame, and must contain the value 0xD5. • Destination Address - The LSB determines if the address is an individual/ unicast (0) or group/multicast (1) address. • It’s the first field that must always be provided.

  6. 40Gbit SGEthernet MAC Frame StructureIEEE 802.3 64 – 1518 Bytes • Source Address – Must always be provided by the client because it’s not modified by the Ethernet MAC. • Length/Type – If the decimal value of this field is 1536 or greater it’s interpreted as a Type field (Indicates if it’s a VLAN frame or PAUSE/MAC ctrl frame). Otherwise it’s interpreted as a Length field and represents the number of bytes in the following Data field.

  7. 40Gbit SGEthernet MAC Frame StructureIEEE 802.3 64 – 1518 Bytes • Data – Varies from 0-1500 Bytes, must always be provided. • Pad – Used to ensure that the frame length is at least 64 bytes in length, and required for successful CSMA/CD operation. • CRC-32-Calculated over the destination address,source address, length/type, data, and pad fields using a 32-bit Cyclic Redundancy Check (CRC). If an incorrect FCS value is received it indicates that the received frame is bad.

  8. 40Gbit SGFPGA Block Diagram - Reminder

  9. 40Gbit SGFPGA Modules Design Destination Address Module Function: crates legal Ethernet Destination Address according to IEEE std 802.3

  10. 40Gbit SGFPGA Modules Design Source Address Module Function: crates legal Ethernet Source Address according to IEEE std 802.3

  11. 40Gbit SGFPGA Modules Design Length Module • Function: crates legal Ethernet Length according to IEEE std 802.3 • If not supplied with a valid VLAN tag will add 16 bits from in_data

  12. 40Gbit SGFPGA Modules Design Frame Data Creator Module Function: crates Ethernet Frame Data according to Length module and to IEEE std 802.3

  13. 40Gbit SGFPGA Modules Design CRC-32 Module Function: creates Ethernet Cyclic Redundancy Check by establishing calculation over the previous modules outputs and according to IEEE std 802.3

  14. 40Gbit SGFPGA Modules Design Command Unit Module Function: determine which 64/66 command will be injected after the currently transmitted Packet

  15. 40Gbit SGFPGA Modules Design Frame Delay Function: Used to align Frames and add Latency in favor of CRC calculations (if needed)

  16. 40Gbit SGFPGA Modules Design LastSlice Function: Deals with last 64 bits segment of packet and special cases for it

  17. 40Gbit SGFPGA Modules Design 10G-baseR PHY Module PCS : Physical Coding Sub-layer is a digital logic that prepares parallel data for transmission across a physical medium or restores data to original form (ex. Encoding and Scrambling) PMA: Physical Medium Attachment converts digital data to serial analog stream. Connects to physical medium (Parallel to serial conversion)

  18. 40Gbit SG Mini-Project vidio“Binary Counter “

  19. 40Gbit SG Gantt Chart

  20. 40Gbit SG Gantt Chart – In Depth

  21. 40Gbit SG Questions ? Thank you …

  22. 40Gbit SG Backup

  23. 40Gbit SGBackground • Debugging a modern communication chip requires the ability to generate high speed L1 & L2 Ethernet signals on all ports of the chip. • High speed Ethernet signals (41.25 GHz) can be generated by commercial tools, e.g. IXIA, however they are expensive and deal mainly with higher software layers.

  24. 40Gbit SGTechnicalSpecifications • Software Tools: • Quartus Design Tool • Altera USB Programming Tool • The Mega Core Functions (PHY+PCS+PMA) • Hardware: • Altera Stratix IV with 10Gbps Ser-Des • Board with SFP+ Modules 10Gbps • Link Partner – IXIA • PC • Fiber Optic Cable • Hardware Programming Language: VERILOG • Output: Valid 802.3 Ethernet Packets Transmitted by 64b/66b coding protocol

  25. 40Gbit SGRisks • Board not arriving on time – We ordered the board 2 months ahead. • Defective modules – Ordering two boards. • Knowledge gap – Mini project with Altera.

  26. 40Gbit SGSystem Block Diagram Final 40Gps Signal Generator

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