IBM logo must not be moved, added to, or altered in any way.

1. IBM logo must not be moved, added to, or altered in any way. An Integrated Methodology for SoC Design, Verification, and Application Development Amir Hekmatpour, Dave Roberts, Michael D. Hale ASIC & IP Development IBM Microelectronics Robert Devins Worldwide Design Center IBM Microelectronics

2. Outline: • SoC Evolution - Functionality & Complexity • Why an integrated methodology?? • Correct by Application - CbA: • Open Simulation System • Virtual-Board (Vboard) • Correct by Verification - CbV • An Assertion-based Approach • Block-level Assertion Generation • Model-based System Architecture • Correct by Design - CbD • Correct by Construction - CbC

3. Needed: Design Productivity Improvement

4. Why an Integrated Methodology?

5. Impact of being late to market

6. Industry Standard Methodology

7. IBM Integrated ASIC Methodology

8. Time to Market: Design Time Challenges

9. IBM: First TimeRight Summary Extracting the benefits of advanced technologies is becoming more § and more difficult with time – Designs are becoming more complex – Process technologies are becoming more complex – The interactions between Design and Technology more subtle The IBM advantage: § – Vertically integrated (technology, tools, designs) Complete, fully integrated, process smart tool set and methodology – – High end server designs that debug the methodology – Strategic to IBM ’ s success The IBM result: § – A high percentage of first time right silicon – Time to market leadership – #1 ASIC provider world wide 4 years running

10. SoC Methodology: Overview • "SoC First-Time-Right" = • IBM Blue Logic design methodology, tools, and services + • SoC Methodology (presented here) • SoC methodology = • An improved co-simulation environment + • A block-level assertion-based functional verification + • Correct by design & correct by construction design practices

11. Correct by Application: Open Simulation Platform

12. Correct by Application:IC-Sim Adapter Overview • CPU View • CPU Clients are Native-Executable or ISS-based • Delivers software originated transactions (load/store/cache ops) • Returns transaction responses and exceptions • Standardized interface enables variety of CPU/BFM's (PPC, ARM, or external processor), multiple instances per system • Enables high performance, visibility and control of CPUinteractions • Modeling View • Models manipulate I/O, allow internal and external C-modeling • Modeling Clients are C/C++ or SystemC, multiple instances per system • Transactions delivered to internal Slave models from CPU's • Internal Master models deliver transactions to the Busmodels • Chip I/O controlled by external models

13. Correct by Application:Real World Modeling Virtual Board interact/interface with real world devices/models Device Under Verification/Analysis ATM Cells Executing..... RTOS Application or Diagnostic Programs Ethernet Packets Video Data IIC, Serial Ports, etc

14. Correct by Application:Vboard Co-modeling System

15. Correct by Application:PPC4xx In-Chip Example Debugger: RiscWatch for IBM ISS, Native exec (gdb), or other ISS debugger Client Process Native C/C++ or ISS "CPU" LD/ST/Cache DCR R/W Exception Handling Socket, Shared or DLL PLI/Cycle CPU Interface (IC-Sim) Simulator (DUT) Sideband (Exceptions resets,ect) DCR Master PLB3/4 Master CPU 405 or 440 Plugin Wrapper Resets CR/NCR Ints PLB3/4 DCR Reset UIC PLB Core PLB Core DCR Core

16. Correct by Application:IC-Sim C-Model Structure enum {dcr_rw0,dcr_rw1}; void ICS_Client_Main(void) { ICS_Schedule_Transaction(dcr_rw0, ICS_DCR_TRANS | ICS_RW | ICS_RETAIN); while(1) { // run model forever ICS_Yield(&wakeup); if(wakeup.flags==ICS_W) ICS_Acknowledge_Transaction(dcr_rw,0); . . . } }

17. Correct by Verification:ABV SoC Validation

18. Block-Level Coverage-Driven Assertion-Based Verif. Design (SLD, HDL, RTL) & Analysis Define & Define & Analyze Define & Generate Generate Generate Assertion Assertions Compliance Verification Coverage Environment & Quality Models Parameters Static & Dynamic Verification Check Blocks against Spec Verify System against Spec Interface & Functional Coverage Analysis

19. Correct by Verification:Block-level Assertions

20. Correct by Verification:Assertion Generation

21. Correct by Verification:Model-Based Architecture Auto Assertion Generation (Blocks) & Optimization Assertion Schema(s) => Serve as generation models Dynamic Instantiation based on Assertion Schema Efficient regeneration and what-if analysis

22. An Assertion-Based Coverage-Driven Environment Define Assertions Extract Assertions Parse HDL/RTL IP/SOC HDL/RTL Update AssertDB Identify missing Asserts Generate Asserts Analyze Asserts Update AssertDB missing boundry asserts AssertDB Classify Type, Severity Known IP functional asserts Generate IP/SOC Quality Rprt Compliance & Quality Reports Sim. Env. Design & Verification Controls Generate SimControls IP Assert KB Env. Config. Functional KB Models (IP, Bus) IP Test Benches Generate TestBench Generate Cvg Model Test Generators Interconnect, Toggle, HDL/RTL Assertions Models Transaction (should, shouldn't) Tests Simulators (Cycle & Event) Formal Verification Semi-Formal Verification WebCover Analyze Logs CoverageDB Cvg Analysis & Reports Extract Cvg

23. Correct by Design: Outline • "First Time Right" • Focus on putting effort up front to prevent design problems, rather than applying effort later to detect and fix them • The main CbD techniques • setup & infrastructure • abstraction • single source • IP reuse.

24. Correct by Design:Setup & Infrastructure

25. Correct by Design:Abstraction

26. Correct by Design:Single Source

27. Correct by Design:IP Re-Use

28. Correct by Construction: Outline • Reduce Design Iterations • Well defined & Repeatable IP Integration • Platform Based Design (PBD) Approach • CbC tools • Platform Express - Mentor Graphics • CORAL - IBM Research • CbC's IP Encapsulation Enables ReUse

29. Correct by Construction: Traditional Approach • Traditional Approach • Multiple views per IP • Single use of each view • Duplication of effort • Each view needs to be configured, connected.... • Increased chance of inconsistency between views • Work effort is in creating the design for each view IP1s IP2s Simulation IP5s IP4s IP3s IP1a IP2a Analysis IP5a IP4a IP3a IP1m IP2m Model IP5m IP4m IP3m

30. Correct by Construction: Integrated IP View IP Container • Contemporary Methods • One view per IP - Multiple use • Encapsulation of reuse • One design needs to be connected, each view is generated from one source • Increased consistency • Work effort is in creating the container which encapsulates the IP into one "design" view. • Significant information can be obtained from a single source • Memory Maps, IP & System Level documentation, external stimulus requirements IP1 IP2 IP3 IP5 IP4 IP IP IP IP IP IP IP IP IP IP IP IP IP IP IP Simulation View Models View Analysis View

31. Summary: • An integrated methodology for SoC • design, verification, and Application Dev. • CbA • Open simulation environment • industry standard modeling languages • provides a virtual board system model • An Assertion-based Correct by Verification • The block-level assertion generation • improves the functional verification • interconnect analysis & protocol compliance checking. • The CbD & CbC tools and techniques • enable & enforce coherent & efficient design practices.