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PHOBOS Trigger Logic

PHOBOS Trigger Logic. L0 Logic. All times are relative to PNPP wide. R. Connected to a register. N. Connected to a scaler. Twisted pair dECL lines. 55. 108. 206. 60. 210. G12.10. G12.5. G5.10. G5.09. G12.4. G12.6. G5.09. G5.09. G12.2. G12.3. G12.1. C2.14. C2.10. C2.11.

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PHOBOS Trigger Logic

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  1. PHOBOS Trigger Logic A. Sukhanov

  2. L0 Logic All times are relative to PNPP wide R Connected to a register N Connected to a scaler Twisted pair dECL lines 55 108 206 60 210 G12.10 G12.5 G5.10 G5.09 G12.4 G12.6 G5.09 G5.09 G12.2 G12.3 G12.1 C2.14 C2.10 C2.11 C2.09 C2.13 C2.12 C2.16 4 ns 4 ns 64 ns 43? 44 288 220us 44 164? 408 124 1800us 56 FI 68 452 G9.B 114 26 ns D D C C D G6C G11C G11B G6A G6B C Measured Pause Interval for pileup control TML0 MPI 1/N R R N TOF ADC GateCAT ADC Gate 1/N R CO.2 1/N R CO.5 CC 1/N R Paddle ADC Gate ADC 6 R d Trig TDC C3.16 L0Pulse R ZCAL+PaddlesTDC Start TDC 4+5 1 CO.1 R TOF+PaddlesTDC Start CAT ICAS N R N L0 Time=0 L0 to L1 L1CI.0 CO.0 ! R Heartbeat Veto L0 74 R Pedestal N Busy from L1 L1C0.15 R CI.15 Si Cosmic Busy from FB. NIMOUT 0 R ZGate PNPP Wide d ZCAL ADC Gate ADC 7 CO.3 D R ZExclGate ZCAL C 2520 in the case of FC 2 ms normal CO.4 CO.10 L0 FanOut CO.11 Non ZCAL trigger R TOF Cal CO.8 Exclusive ZCAL trigger PCAL main gate CO.9 PCAL cosmic gate Changes: 8/28/00 front of the ZCAL ADC made earlier by 16 ns 11/02/00 TOFrig applied to G11C bypassing 40ns delay to gain 40 ns for TOF cosmic 11/13/00 Drawing error, swapped C2.10<->C2-11 7/04/01 G12 input changes to fit the flat cable arrangement 7/05/01 Paddle ADC Gate G12.3-G6B cable delay changed from 48 to 16ns. G6B changed to 140ns 7/06/01 Paddle ADC Gate G12.3-G6B cable delay changed from 16 to 4ns. G6B changed to 152ns 11/13/02 Paddle ADC Gate G6B is taken from G12.2 not G12.6. 11/14/02 Added MPI, prescalers T[0:3] 01/10/03 Added PCAL gates A. Sukhanov

  3. L1 logic 1000 1060 55 1 D 526 114 2520 5000 G12.13 C D D C C G11A R Connected to a register N Connected to a scaler TML1 Twisted pair dECL lines 1/N Prescaler 0.0-3 L0from G11B 0 R 1/N Pn*Pp(2)from A8B 1 0.4-7 R R N 1/N Fast Clear CO.2 ZTrigfrom D7C 2 0.8-11 R 1/N Busy Pn*Pp Narrowfrom A2B 3 0.12-15 Veto to L0 R CO.15 1/N L1 N L1 to EMS Silicon (CI.0) Vtxfrom A10B 4 3.0-3 CO.1 R 1/N Centralityfrom A12B 5 3.4-7 R 1/N Event Accepted R N L1 CVtxfrom A12A 6 3.8-11 CO.0 R L1 to DAQ (EMM.CI.0) 1/N 3.12-15 Trig TDC (C3.8) Heartbeatfrom C10C 7 R 1/N Note. Before 07/12/00 the G11A output has been at 180 ns Changes: 5/29/01. Drawing error. G11B to G11A 7/4/01. G12.13, CO.2 PN*PP wide PN*PP narrow L0 Fast Clear L1 A. Sukhanov

  4. EMM 08) Token7 15) Token0 14) Token1 13) Token2 12) Token3 11) Token4 10) Token5 04) Trig Pulse 09) Token6 05) CO5 03) SiL2 02) SiL1 00) Busy 01) HShk 06) HShk 16) GND 07) TokStrobe 02) 05) 01) 03) 07) 06) 04) Red Orange Yellow Green Blue Purple + Cin - 16 GND 15 CI[15] 14 CI[14] 13 CI[13] 12 CI[12] 11 CI[11] G10 10 CI[10] 9 Busy Forced 06 Trig0 8 Busy PHTMS 07 MDCL2 7 Busy VROC 08 SynCal 6 Busy FBROC 09 Busy L0 5 Busy Si 10 Busy L1 4 Busy L1 11 Busy Si 3 Busy L0 12 Busy FBROC 2 SynCal 13 Busy VROC 1 MDCL2 14 Busy PHTMS 0 Trig0 15 Busy Forced - Cout + To VMERocand FastBus + G5 - SiL2, SiL2 G8.2:3 • Modifications: • 04/17/04 G10 Numbering starts from 0 SiL1, SiL1 G8.0:1 BusyEMM. G9.3 A. Sukhanov

  5. TML0 8) Heartbeat 13) ZTrig 12) PNPP 11) SiCosm 10) 100 Hz 9) FBCosm 14) CC 8) 7) 4) 3) 2) 1) 0) 6) 16) GND 5) 7) BRevolut 15) Veto 6) BUp 18) 17) 16) 15) 14) 13) 12) 11) 2) N/A 9) 0) N/A 1) Bucket3 19) 3) YDown 4) YUp 5) BDown 10) 1) L0 pulse 12) L0In 16) GND 0) L0 2) L0 pulse 9) PCALCosm 15) Veto L0 5) FBCosm 8) PCALColl 6) HiPrio 7) TinV 4) ZGateExcl 3) ZGate 14) dbg.DP[0] 13) dbg.L0Clk 10) L0 11) L0 + L0_CIn - + DP - CC clocked triggers V124B.6 Blue Bucket #1. Used to clear Bucket counter in L0 V124B.3 Blue Polarization Up V124B.4 Blue Polarization Down V124Y.3 Yellow Polarization Up V124Y.4 Yellow Polarization Down - L0_COut + V124B.7 Every third blue bucket, used to count Bucket Counter in L0 17 G05 16 x x x 15 x x x 14 x x x 13 x x x Visual Sc13 12 x x x L0Trg H4.7 10 x x x ?White cable 09 x x x PCALCosm 08 x x x PCALColl TinV G12 08 HiPrio 07 TOF Excl ADC Gate 06 ZCAL ADC Gate 05 ZCAL ADC Gate 04 TOF+Paddle ADC Gate 03 • Modifications: • 01/08/04 Correct L0->G5 • 04/14/04 Polarization bits on DP 02 Paddle+ZCALTDC start 01 To L1 logic, TOF TDC start A. Sukhanov

  6. TML1 7) Pr7 0) Lvl0 1) Pr1 2) Pr2 3) Pr3 5) Pr5 6) Pr6 8) 4) Pr4 10) 12) 13) 14) 15) Veto 16) GND 11) 9) 8) PrO.1 7) PrO.0 15) BusyL1 14) PrO.7 12) PrO.5 11) PrO.4 10) PrO.3 13) PrO.6 1) L1Pulse 5) PrTest 16) GND 0) Lvl1 9) PrO.2 2) FastClear 4) PrQ1 3) L1in 6) L1OR + L1_CIn - - L1_COut + G12.10 PrQ1 G12 16 L1in 15 • Modifications: • 04/17/04 Show connection for BusyL1 Fast Clear 14 L1pulse 13 L1 12 A. Sukhanov

  7. Si L0/L1 73us 73us 41us 41us G12.11 G8.12 G12.9 G8.13 G8.15 G8.14 G8.0 G8.3 G8.2 G8.1 G5.4 G5.3 560us 2560us G7C G7D G4D Calibration mode Time=0 TTL/NIM NIM/ECL EMM MDC1 SynCal MDC1 L1 Si L1 CI.9 CO.2 MDC2 L1 MDC2 SynCal MDC1 L2 MDC1 INT L2 Si L2 CO.3 CI.8 MDC2 L2 MDC2 INT L2 A. Sukhanov

  8. NIM Crates 00 01 02 G10 G12 Model 4616 03 726 PS 04 To L1 logic, TOF TDC start L0 01 Translator 05 Paddle+ZCALTDC start 02 06 00 00 00 00 TOF+Paddle ADC Gate 03 07 01 01 01 01 ZCAL ADC Gate 04 08 02 02 02 02 ZCAL ADC Gate 05 09 03 03 03 03 TOF Excl ADC Gate 06 10 04 04 04 04 HiPrio 07 11 05 05 05 05 TinV 08 12 G12.12 L1 06 06 06 06 SynCal 09 13 For SiCaL MDCL2 07 07 07 07 TML1.CO15 Busy L1 10 14 00 00 MDC* 11 15 01 01 L1 12 L1 02 02 L1pulse 13 03 03 Fast Clear 14 04 04 L1in 15 05 05 PrQ1 16 06 06 07 07 08 08 09 09 To EMM 10 10 11 11 VROC CO13 BusyVROC 12 12 FB CO13 BusyFB 13 13 14 14 15 15 16 16 08 08 08 08 G11.02 Out BusyL0 09 09 09 09 G12.10 Out BusyL1 10 10 10 10 G09.03 Out BusySi 11 11 11 11 • Modifications: 12 12 12 12 13 13 13 13 14 14 14 14 G06.03 Out BusyForce 15 15 15 15 A. Sukhanov

  9. FASTBUS + Cin - 16 GND LEMOs LEDs 15 CI[15] 14 CI[14] G L1 Busy 13 CI[13] NIM In 1 R L2 Error 12 CI[12] 2 G L3 EMMData 11 CI[11] 3 G L4 Init 10 CI[10] Reset 9 HandShake NIM Out 1 Busy 8 TokClk 2 Error 7 Token[07] 3 Data Transfer 6 Token[06] 5 Token[05] From EMM CO[06:15] 4 Token[04] 3 Token[03] Description Legend: L refers to LED, N – to NIM LEMO L4 ON: init_crate OFF: Run stopped N2 L2 : 1: 1)Read/Write mismatch, slot %d (r=%d,w=%d). DP=%x 2)ERROR: Load Next Event in slot %d\n",slot 0: Finished sending event L3: 1: start copying VME block9 0: finished VME block N3, L4 1: Start sending event 0: Finished sending event N1,L1 1: End of the Sparse Data Scan 0: Finished VME block 2 Token[02] 1 Token[01] 0 Token[00] + COut - 16 GND 15 Ack 14 Dbg_HShck 13 RQ Busy VROC to EMM G10.13 12 Dbg_TokClk 11 Dbg_Trans 10 CO[10] 9 CO[09] 8 CO[08] 7 CO[07] 6 CO[06] 5 CO[05] • Modifications: • Shown Cin/COut 4 CO[04] 3 CO[03] 2 CO[02] 1 CO[01] 0 CO[00] A. Sukhanov

  10. Modifications 1/1/4. Cosmetic A. Sukhanov

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