Enhancing Logic Reliability with Redundant Twin Logic Gates

1. Institute of Applied Microelectronics and Computer Engineering Twin Logic Gates – Improved Logic Reliability by Redundancy concerning Gate Oxide BreakdownHagen Sämrow, Claas Cornelius, Frank Sill,Andreas Tockhorn, Dirk Timmermann03.09.2009, Natal University ofRostock

2. Outline • Motivation and Basics • Approaches for reliability enhancements • Gate oxide breakdown • Redundancy strategies • Redundancy on different levels • Results • Discussion • Conclusion / Outlook

3. Motivation – Known approaches Reliability Transient failures Permanent failures Failures occuring at runtime Initial failures

4. Basics – Gate oxide breakdown • Gate oxide breakdown – GOB: • Point of time a conducting path between gate and substrate is generated • Mainly dependent on: • Gate oxide thickness • Electrical field at the gate • Causes: • Sudden extrinsic overvoltage: ESD – Electro-Static Discharge • Slow intrinsic destruction over time: TDDB – Time-Dependent Dielectric Breakdown

5. Basics – TDDB Initial traps Physical mechanism: trap creation Finally: Hard breakdown During operation: generation of overlapping traps R  0 Soft breakdown: Creation of a conducting patch • Increasing current flow • Heat dissipation • Thermal damage

6. Basics – TDDB Finally: Hard breakdown Model by Renovell et al. • Follows new research results • Gate oxide breakdown harms an affected transistor and its associated cell with a modified delay • Whole circuit fails if the timing between the cells is no longer balanced

7. Basics – Scaling issues • Scaling increases the gate oxide breakdown problems: • Increasing number of transistors within a die • Decreasing gate oxide thickness • Increase of the electrical field due to non-ideal supply voltage scaling

8. Redundancy strategies • Basic multiplier • Block duplication • Gate duplication • Transistor duplication

9. Simulation setup • Wallace multiplier • Transistor level simulations with HSpice • Industrial 65 nm gate library • Gate oxide breakdown model of Renovell et al. • Implementation of cells with transistors with standard threshold voltage (SVT) and high threshold voltage (HVT)

10. Results – No defects

11. Results – Reliability with defects Simulation results

12. Results – Discussion Whyisthegatelevelduplication (LogicTwin Gates) betterthantransistorduplication? • Bothimplementationonlydiffer in theduplicationofthetransistorstacks • Defect_net 2 ischargedto a voltagerelatedtothe GOB • Currentflowfromdraintosourceofthemiddletransitorisratherpinched off due tothedefect (highervoltagelevelbetweenlowesttwotransistors) • Increased fall time ofthedefectstack • Transistor duplicatedstacksareslightlyslower due tothecross links

13. Results – Graceful degradation I • Increase of the delay with rising defects

14. Results – Graceful degradation I • Increase of the delay with rising defects due to increased static power consumption

15. Conclusion • Need of design improvements for lifetime reliability • Logic Twin Gates promises the most improvements concerning gate oxide breakdown • Simple integration of Logic Twin Gates into existing design flows and CAD tools • Graceful degradation behavior in the presence of defects

16. Outlook • Partial duplication of most vulnerable gates or transistors • Usage of benchmark circuits • Investigation of the impact of soft breakdowns