Progettazione di circuiti e sistemi VLSI

1. Progettazione di circuiti e sistemi VLSI Anno Accademico 2007-2008 Lezione 15 Riepilogo 1

2. Challenges in Digital Design “Macroscopic Issues” • Time-to-Market • Millions of Gates • High-Level Abstractions • Reuse & IP: Portability • Predictability • etc. …and There’s a Lot of Them! • “Microscopic Problems” • • Ultra-high speed design • Interconnect • • Noise, Crosstalk • • Reliability, Manufacturability • • Power Dissipation • • Clock distribution. • Everything Looks a Little Different ?

3. Productivity Trends 10,000,000 100,000,000 (M) 10,000 100,000 Logic Tr./Chip 1,000,000 10,000,000 Tr./Staff Month. 10,000 1,000 100,000 1,000,000 100 1,000 58%/Yr. compounded Complexity 10,000 100,000 Productivity (K) Trans./Staff - Mo. Complexity growth rate 10 100 Logic Transistor per Chip 1,000 10,000 1 10 x x 100 1,000 21%/Yr. compound x x x x x Productivity growth rate 1 0.1 x 10 100 0.1 0.01 1 10 0.01 0.001 1981 1983 1985 1987 1989 1991 1993 1995 1997 1999 2001 2003 2005 2007 2009 Source: Sematech Complexity outpaces design productivity Courtesy, ITRS Roadmap

4. Design Metrics • How to evaluate performance of a digital circuit (gate, block, …)? • Cost • Reliability • Scalability • Speed (delay, operating frequency) • Power dissipation • Energy to perform a function

5. Cost of Integrated Circuits • NRE (non-recurrent engineering) costs • design time and effort, mask generation • one-time cost factor • Recurrent costs • silicon processing, packaging, test • proportional to volume • proportional to chip area

6. Mapping between analog and digital signals V V out “ 1 ” OH Slope = -1 V V OH IH Undefined Region V Slope = -1 IL V OL “ 0 ” V OL V V V IL IH in

7. A Modern CMOS Process Dual-Well Trench-Isolated CMOS Process

8. CMOS Process at a Glance Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers

9. Design Rules • Interface between designer and process engineer • Guidelines for constructing process masks • Unit dimension: Minimum line width • scalable design rules: lambda parameter • absolute dimensions (micron rules)

10. Progettazione di circuiti e sistemi VLSI Anno Accademico 2007-2008 Lezione 3 Dispositivi e modelli

11. Diode Model

12. Current-Voltage RelationsLong-Channel Device

13. A model for manual analysis

14. Dynamic Behavior of MOS Transistor

15. Gate Capacitance Cut-off Resistive Saturation Most important regions in digital design: saturation and cut-off

16. Impact of Interconnect Parasitics • Interconnect parasitics • reduce reliability • affect performance and power consumption • Classes of parasitics • Capacitive • Resistive • Inductive

17. CMOS Inverter Load Characteristics

18. CMOS Inverter VTC

19. CMOS Inverter Propagation DelayApproach 1

20. CMOS Inverter Propagation DelayApproach 2

21. Inverter Chain In Out CL • If CL is given: • How many stages are needed to minimize the delay? • How to size the inverters? • May need some additional constraints.

22. Apply to Inverter Chain In Out CL 1 2 N tp = tp1 + tp2 + …+ tpN

23. Optimal Tapering for Given N • Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N • Minimize the delay, find N - 1 partial derivatives • Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1 • Size of each stage is the geometric mean of two neighbors • each stage has the same effective fanout (Cout/Cin) • each stage has the same delay

24. Optimum Delay and Number of Stages When each stage is sized by f and has same eff. fanout f: Effective fanout of each stage: Minimum path delay

25. Optimum Effective Fanout f Optimum f for given process defined by g fopt = 3.6 forg=1

26. Dynamic Power Dissipation Vdd Vin Vout C L 2 Energy/transition = C * V L dd 2 Power = Energy/transition * f = C * V * f L dd Not a function of transistor sizes! Need to reduce C , V , and f to reduce power. L dd

27. Progettazione di circuiti e sistemi VLSI Anno Accademico 2007-2008 Lezione 6 La logica combinatoria

28. Combinational vs. Sequential Logic Combinational Sequential Output = ( ) f In, Previous In Output = ( ) f In

29. Static CMOS Circuit At every point in time (except during the switching transients) each gate output is connected to either V or V via a low-resistive path. DD ss The outputs of the gates assumeat all timesthevalue of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.

30. Constructing a Complex Gate

31. CMOS Properties • Full rail-to-rail swing; high noise margins • Logic levels not dependent upon the relative device sizes; ratioless • Always a path to Vdd or Gnd in steady state; low output impedance • Extremely high input resistance; nearly zero steady-state input current • No direct path steady state between power and ground; no static power dissipation • Propagation delay function of load capacitance and resistance of transistors

32. Transistor Sizing Rp Rp 4 4 2 2 Rp Rp A B A B 2 2 Rn Cint Cint CL CL Rn Rn Rn B B A A 1 1

33. Transistor Sizing a Complex CMOS Gate B 8 6 4 3 A C 8 6 4 6 D OUT = D + A • (B + C) A 2 D 1 B 2 C 2

34. Fast Complex Gates:Design Technique 1 • Transistor sizing • as long as fan-out capacitance dominates • Progressive sizing Distributed RC line M1 > M2 > M3 > … > MN (the mos closest to the output is the smallest) InN MN C3 C2 C1 CL In3 M3 In2 M2 Can reduce delay by more than 20%; decreasing gains as technology shrinks In1 M1

35. Fast Complex Gates:Design Technique 2 • Transistor ordering critical path critical path 01 charged charged 1 In1 In3 M3 M3 C1 C2 C2 C1 CL CL 1 1 In2 In2 M2 discharged M2 charged 1 In3 discharged In1 charged M1 M1 01 delay determined by time to discharge CL, C1 and C2 delay determined by time to discharge CL

36. Logical Effort p – intrinsic delay (3kRunitCunitg) - gate parameter  f(W) g – logical effort (kRunitCunit) – gate parameter  f(W) f – effective fanout Normalize everything to an inverter: ginv =1, pinv = 1 Divide everything by tinv (everything is measured in unit delays tinv) Assume g = 1.

37. Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay: h = g f logical effort effective fanout = Cout/Cin Logical effort is a function of topology, independent of sizing Effective fanout (electrical effort) is a function of load/gate size

38. Logical Effort • Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates • Logical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current • Logical effort increases with the gate complexity

39. Logical Effort Logical effort is the ratio of input capacitance of a gate to the input capacitance of an inverter with the same output current g = 5/3 g = 4/3 g = 1

40. Add Branching Effort Branching effort:

41. Summary Sutherland, Sproull Harris

42. Ratioed Logic

43. Active Loads

44. Pass-Transistor Logic

45. Dynamic CMOS • In static circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path. • fan-in of n requires 2n (n N-type + n P-type) devices • Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. • requires on n + 2 (n+1 N-type + 1 P-type) transistors

46. Dynamic Gate off Clk Mp on 1 Clk Out Mp ((AB)+C) Out In1 In2 PDN CL A In3 C Clk Me B off on Clk Me Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1)

47. Cascading Dynamic Gates V Clk Clk Mp Mp Clk Out2 Out1 In In Clk Clk Me Me VTn Out1 V Out2 t Only 0  1 transitions allowed at inputs!

48. Differential (Dual Rail) Domino off on Clk Clk Mp Mkp Mkp Mp Out = AB Out = AB 1 0 1 0 A !A !B B Clk Me Solves the problem of non-inverting logic

49. NORA Logic Clk Me Clk Mp Out1 1  1 1  0 In4 PUN In1 In5 In2 PDN 0  0 0  1 In3 Out2 (to PDN) Clk Mp Clk Me to other PDN’s to other PUN’s WARNING: Very sensitive to noise!