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Progettazione di circuiti e sistemi VLSI

Progettazione di circuiti e sistemi VLSI. Anno Accademico 2010-2011 Lezione 6 18.3.2011 La logica combinatoria. Combinational vs. Sequential Logic. Combinational. Sequential. Output =. (. ). f. In, Previous In. Output =. (. ). f. In.

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Progettazione di circuiti e sistemi VLSI

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  1. Progettazione di circuiti e sistemi VLSI Anno Accademico 2010-2011 Lezione 6 18.3.2011 La logica combinatoria La logica combinatoria

  2. Combinational vs. Sequential Logic Combinational Sequential Output = ( ) f In, Previous In Output = ( ) f In La logica combinatoria

  3. At every point in time (except during the switching transients) each gate output is connected to either V or V via a low-resistive path. DD ss The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. Static CMOS Circuit La logica combinatoria

  4. Static Complementary CMOS VDD In1 PMOS only In2 PUN … InN F(In1,In2,…InN) In1 In2 PDN … NMOS only InN PUN and PDN are dual logic networks La logica combinatoria

  5. NMOS Transistors in Series/Parallel Connection • Transistors can be thought as a switch controlled by its gate signal • NMOS switch closes when switch control input is high La logica combinatoria

  6. PMOS Transistors in Series/Parallel Connection La logica combinatoria

  7. Threshold Drops VDD VDD PUN S D VDD D S 0  VDD 0  VDD - VTn VGS CL CL CL CL PDN VDD 0 VDD |VTp| VGS D S VDD S D La logica combinatoria

  8. Complementary CMOS Logic Style La logica combinatoria

  9. Example Gate: NAND P La logica combinatoria

  10. B A C D Complex CMOS Gate OUT = D + A • (B + C) A D B C La logica combinatoria

  11. Constructing a Complex Gate La logica combinatoria

  12. Cell Design • Standard Cells • General purpose logic • Can be synthesized • Same height, varying width • Datapath Cells • For regular, structured designs (arithmetic) • Includes some wiring in the cell • Fixed height and width La logica combinatoria

  13. Standard Cells N Well Cell height 12 metal tracks Metal track is approx. 3 + 3 Pitch = repetitive distance between objects Cell height is “12 pitch” V DD Out In 2 Rails ~10 GND Cell boundary La logica combinatoria

  14. Standard Cells 2-input NAND gate V DD A B Out GND La logica combinatoria

  15. Stick Diagrams Contains no dimensions Represents relative positions of transistors V V DD DD Inverter NAND2 Out Out In A B GND GND La logica combinatoria

  16. Stick Diagrams Logic Graph A X PUN j C B C X = C • (A + B) i VDD X C i B A j A B A PDN B GND C La logica combinatoria

  17. Two Versions of C • (A + B) A C B A B C VDD VDD X X GND GND La logica combinatoria

  18. Consistent Euler Path X C i VDD X B A j A B C GND La logica combinatoria

  19. OAI22 Logic Graph X PUN A C D C B D VDD X X = (A+B)•(C+D) C D B A A B PDN A GND B C D La logica combinatoria

  20. Example: x = ab+cd La logica combinatoria

  21. Properties of Complementary CMOS Gates Snapshot High noise margins : V and V are at V and GND , respectively. OH OL DD No static power consumption : There never exists a direct path between V and DD V ( GND ) in steady-state mode . SS Comparable rise and fall times: (under appropriate sizing conditions) La logica combinatoria

  22. CMOS Properties • Full rail-to-rail swing; high noise margins • Logic levels not dependent upon the relative device sizes;ratioless • Always a path to Vdd or Gnd in steady state; low output impedance • Extremely high input resistance; nearly zero steady-state input current • No direct path steady state between power and ground; no static power dissipation • Propagation delay function of load capacitance and resistance of transistors La logica combinatoria

  23. Switch Delay Model Req A A Rp Rp Rp Rp Rp Rp A A A B B A Cint Rn CL CL CL Rn Rn Rn Rn B B A A A Cint NOR2 INV NAND2 La logica combinatoria

  24. Input Pattern Effects on Delay • Delay is dependent on the pattern of inputs • Low to high transition • both inputs go low • delay is 0.69 Rp/2 CL • one input goes low • delay is 0.69 Rp CL • High to low transition • both inputs go high • delay is 0.69 2Rn CL Rp Rp B A Rn B Cint CL Rn A La logica combinatoria

  25. Delay Dependence on Input Patterns A=B=10 A=1 0, B=1 A=1, B=10 Voltage [V] time [ps] NMOS = 0.5m/0.25 m PMOS = 0.75m/0.25 m CL = 100 fF La logica combinatoria

  26. Transistor Sizing Rp Rp 4 4 2 2 Rp Rp B A A B 2 2 Rn Cint Cint CL CL Rn Rn Rn B B A A 1 1 La logica combinatoria

  27. Transistor Sizing a Complex CMOS Gate B 8 6 4 3 A C 8 6 4 6 D OUT = D + A • (B + C) A 2 D 1 B 2 C 2 La logica combinatoria

  28. D C B A C3 C2 C1 CL Fan-In Considerations A Distributed RC model (Elmore delay) tpHL = 0.69 Reqn(C1+2C2+3C3+4CL) Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case. B C D La logica combinatoria

  29. tp as a Function of Fan-In quadratic Gates with a fan-in greater than 4 should be avoided. tp (psec) tpHL tp tpLH linear fan-in La logica combinatoria

  30. tp as a Function of Fan-Out All gates have the same drive current. tpNOR2 tpNAND2 tpINV tp (psec) Slope is a function of “driving strength” eff. fan-out La logica combinatoria

  31. tp as a Function of Fan-In and Fan-Out • Fan-in: quadratic due to increasing resistance and capacitance • Fan-out: each additional fan-out gate adds two gate capacitances to CL tp = a1FI + a2FI2 + a3FO La logica combinatoria

  32. Fast Complex Gates:Design Technique 1 • Transistor sizing • as long as fan-out capacitance dominates • Progressive sizing Distributed RC line M1 > M2 > M3 > … > MN (the mos closest to the output is the smallest) InN MN C3 C2 C1 CL In3 M3 In2 M2 Can reduce delay by more than 20%; decreasing gains as technology shrinks In1 M1 La logica combinatoria

  33. Fast Complex Gates:Design Technique 2 • Transistor ordering critical path critical path 01 charged charged 1 In1 In3 M3 M3 C2 C2 C1 C1 CL CL 1 1 In2 In2 M2 discharged M2 charged 1 In3 discharged In1 charged M1 M1 01 delay determined by time to discharge CL, C1 and C2 delay determined by time to discharge CL La logica combinatoria

  34. CL CL Fast Complex Gates:Design Technique 3 • Isolating fan-in from fan-out using buffer insertion La logica combinatoria

  35. Fast Complex Gates:Design Technique 4 • Reducing the voltage swing • linear reduction in delay • also reduces power consumption • But the following gate is much slower! • Or requires use of “sense amplifiers” on the receiving end to restore the signal level (memory design) tpHL= 0.69 (3/4 (CL VDD)/ IDSATn ) = 0.69 (3/4 (CL Vswing)/ IDSATn ) La logica combinatoria

  36. Sizing Logic Paths for Speed • Frequently, input capacitance of a logic path is constrained • Logic also has to drive some capacitance • Example: ALU load in an Intel’s microprocessor is 0.5pF • How do we size the ALU datapath to achieve maximum speed? • We have already solved this for the inverter chain – can we generalize it for any type of logic? La logica combinatoria

  37. Buffer Example In Out CL 1 2 N (in units of tinv) For given N: Ci+1/Ci = Ci/Ci-1 To find N: Ci+1/Ci ~ 4 How to generalize this to any logic path? La logica combinatoria

  38. Logical Effort p – intrinsic delay (3kRunitCunitg) - gate parameter  f(W) g – logical effort (kRunitCunit) – gate parameter  f(W) f – effective fanout Normalize everything to an inverter: ginv =1, pinv = 1 Divide everything by tinv (everything is measured in unit delays tinv) Assume g = 1. La logica combinatoria

  39. Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay: h = g f logical effort effective fanout = Cout/Cin Logical effort is a function of topology, independent of sizing Effective fanout (electrical effort) is a function of load/gate size La logica combinatoria

  40. Logical Effort • Inverter has the smallest logical effort and intrinsic delay of all static CMOS gates • Logical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current • Logical effort increases with the gate complexity La logica combinatoria

  41. Logical Effort Logical effort is the ratio of input capacitance of a gate to the input capacitance of an inverter with the same output current g = 5/3 g = 4/3 g = 1 La logica combinatoria

  42. Logical Effort of Gates La logica combinatoria

  43. Add Branching Effort Branching effort: La logica combinatoria

  44. Multistage Networks Stage effort: hi = gifi Path electrical effort: F = Cout/Cin Path logical effort: G = g1g2…gN Branching effort: B = b1b2…bN Path effort: H = GFB Path delay D = Sdi = Spi + Shi La logica combinatoria

  45. Optimum Effort per Stage When each stage bears the same effort: Stage efforts: g1f1 = g2f2 = … = gNfN Effective fanout of each stage: Minimum path delay La logica combinatoria

  46. Optimal Number of Stages For a given load, and given input capacitance of the first gate Find optimal number of stages and optimal sizing Substitute ‘best stage effort’ La logica combinatoria

  47. Logical Effort From Sutherland, Sproull La logica combinatoria

  48. Method of Logical Effort • Compute the path effort: F = GBH • Find the best number of stages N ~ log4F • Compute the stage effort f = F1/N • Sketch the path with this number of stages • Work either from either end, find sizes: Cin = Cout*g/f Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999. La logica combinatoria

  49. Summary Sutherland, Sproull Harris La logica combinatoria

  50. Power • If well designed, the dynamic power prevails • P=α01 CL VDD2 α01 is activity factor = 0.5 for the inverter La logica combinatoria

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