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未经作者允许，请勿发布该文档！ yingqichen@sjtu

未经作者允许，请勿发布该文档！ yingqichen@sjtu.edu.cn. VHDL. Simulation & Synthesis. Agenda. Other Features in VHDL Generate Assert Function Overloading FILE IO. Generate Example (1). 32-bit Bus. RAM0. 8-bit Bus. 8-bit addr. ram32 : ram_0 :static_ram

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未经作者允许，请勿发布该文档！ yingqichen@sjtu

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  1. 未经作者允许，请勿发布该文档！yingqichen@sjtu.edu.cn未经作者允许，请勿发布该文档！yingqichen@sjtu.edu.cn

  2. VHDL Simulation & Synthesis

  3. Agenda Other Features in VHDL • Generate • Assert • Function Overloading • FILE IO

  4. Generate Example (1) 32-bit Bus RAM0 8-bit Bus 8-bit addr ram32 : ram_0 :static_ram portmap (cs_b,we_b,oe_b, abus(7 downto 0), dbus(7 downto 0)); ram_1 :static_ram portmap (cs_b,we_b,oe_b, abus(7 downto 0), dbus(15 downto 8)); ram_2 :static_ram portmap (cs_b,we_b,oe_b, abus(7 downto 0), dbus(23 downto 16)); ram_3 :static_ram portmap (cs_b,we_b,oe_b, abus(7 downto 0), dbus(31 downto 24)); endgenerate ram32; RAM1 8-bit Bus 8-bit addr RAM2 8-bit Bus 8-bit addr RAM3 8-bit Bus 8-bit addr

  5. Generate Example (2) 32-bit Bus RAM0 8-bit Bus 8-bit addr ram32 : for i in 3 downto 0 generate ram :static_ram portmap (cs_b,we_b,oe_b, abus(7 downto 0), dbus(8*i+7 downto 8*i)); endgenerate ram32; RAM1 8-bit Bus 8-bit addr RAM2 8-bit Bus 8-bit addr RAM3 8-bit Bus 8-bit addr

  6. Generate Label: for ParameterName in Range generate ConcurrentStatements... endgenerate [Label]; Label: if Condition generate ConcurrentStatements... endgenerate [Label];

  7. a(0)b(0)c_in(1) a(1)b(1) c_in(2) a(2)b(2) c_in(3) c_in(win-1) a(wid-1)b(wid-1) HA sum(0) sum(1)sum(2) sum(wid-1) carry Generate Example (3) FA a(0)a(1)a(2)…a(wid-1) b(0)b(1)b(2)…b(wid-1) Adder FA … sum(0)sum(1)sum(2)…sum(wid-1)carry … … … FA

  8. a(0)b(0)c_in(1) a(1)b(1) c_in(2) a(2)b(2) c_in(3) c_in(win-1) a(wid-1)b(wid-1) HA sum(0) sum(1)sum(2) sum(wid-1) carry Generate Example (4) FA adder : for i in 0 to wid-1 generate ls_bit : if i = 0 generate ls_cell : HA port map (a(0), b(0), sum(0), c_in(1));endgenerate lsbit; middle_bit : if i > 0 and i < wid-1 generate middle_cell : FA portmap (a(i), b(i), c_in(i), sum(i), c_in(i+1));endgenerate middle_bit; ms_bit : if i = wid-1 generate ms_cell : FA portmap (a(i), b(i), c_in(i), sum(i), carry);endgenerate ms_bit; endgenerate adder; FA … FA

  9. Agenda • Generate • Assert • Function Overloading • FILE IO

  10. Assert • Definition [Label:]assertCondition [report StringExpression] [severity Expression]; • Note • The message is written when the Condition isFalse! • The default string for report clause is “Assertion violation” • The default string for severity clause is “ERROR”

  11. Concurrent Assertions & Concurrent Procedure Calls concurrent assertions Label : assertconditionreporterror_string severityseverity_value; concurrent procedure calls Label : processbeginassertconditionreporterror_stringseverityseverity_value;wait[ sensitivity_clause ] ;endprocess Label;

  12. Assert Example (1) assertnot (Reset = '0' and Set = '0') report"R-S conflict" severityFailure;

  13. Assert Example (2)

  14. Severity_level type severity_level is (note, warning, error, failure); (In standard.vhd)

  15. Agenda • Generate • Assert • Function Overloading • FILE IO

  16. Function Overloading • VHDL allows two subprograms to have the same name, provided the number or base types of parameters differs

  17. Function Overloading (Example 1) functionFoo(value : bit) return boolean; functionFoo(value : std_logic) return boolean;

  18. Function Overloading (Example 2) function "+" (arg1, arg2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; function "+" (L, R: UNSIGNED) return UNSIGNED; function "+" (L, R: SIGNED) return SIGNED;

  19. Function Overloading (Example 3) FUNCTION "+" (arg1, arg2:UNSIGNED) RETURN UNSIGNED IS CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length); VARIABLE lt : UNSIGNED(1 TO ml); VARIABLE rt : UNSIGNED(1 TO ml); VARIABLE res : UNSIGNED(1 TO ml); VARIABLE carry : STD_LOGIC := '0'; VARIABLE a,b,s1 : STD_LOGIC; -- Unsigned arithmetic addition of two vectors. MSB is Left. ATTRIBUTE synthesis_return OF res:VARIABLE IS "ADD" ; BEGIN lt := zxt( arg1, ml ); rt := zxt( arg2, ml ); FOR i IN res'reverse_range LOOP a := lt(i); b := rt(i); s1 := a + b; res(i) := s1 + carry; carry := (a AND b) OR (s1 AND carry); END LOOP; RETURN res; END; FUNCTION "+" (arg1, arg2 :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS CONSTANT ml : INTEGER := maximum(arg1'length,arg2'length); VARIABLE lt : STD_LOGIC_VECTOR(1 TO ml); VARIABLE rt : STD_LOGIC_VECTOR(1 TO ml); VARIABLE res : STD_LOGIC_VECTOR(1 TO ml); VARIABLE carry : STD_LOGIC := '0'; VARIABLE a,b,s1 : STD_LOGIC; -- Unsigned arithmetic addition of two vectors. MSB is Left. ATTRIBUTE synthesis_return OF res:VARIABLE IS "ADD" ; BEGIN lt := zxt( arg1, ml ); rt := zxt( arg2, ml ); FOR i IN res'reverse_range LOOP a := lt(i); b := rt(i); s1 := a + b; res(i) := s1 + carry; carry := (a AND b) OR (s1 AND carry); END LOOP; RETURN res; END;

  20. Function Overloading (Example 4) function "+" (a, b : byte) return byte isbeginreturnint_to_byte(byte_to_int(a) + byte_to_int(b));end "+"; X"1000_0010" + X"0000_FFD0" "+" (X"1000_0010", X"0000_FFD0")

  21. Agenda • Generate • Assert • Function Overloading • FILE IO • Text File • Binary File

  22. Read/Write Text File Read From Text File Disk File Line variable 12123122341 Awfe 011100010 ---------- Data Object Read() ReadLine() 1001011011 Disk File Write To Text File Line variable 12123122341 Awfe 011100010 ---------- Data Object Write() WriteLine() 1001011011

  23. Read/Write Text File Steps • Step 1 Define user data object, DataObj • Step 2 Define Line object, LineObj variable LineObj: line; • Step 2 Define TextFile object, FileObj file FileObject: text is in "FileName"; file FileObject: text is out "FileName"; • Step 4 Read/Write Data • Read readLine(FileObj, LineObj); read(LineObj, DataObj); • Write Write(LineObj, DataObj); WriteLine(FileObj, LineObj);

  24. Read/Write Text File (Example) library ieee; use ieee.std_logic_1164.all; use std.textio.all; entity text_file_read is end text_file_read; architecture text_file_read_a of text_file_read is begin process variable bv: bit_vector(3 downto 0); variable ln_in: line; variable ln_out: line; file file_in: text is in "text1.dat"; file file_out: text is out "text2.dat"; begin loop exit when endfile(file_in); readline(file_in, ln_in); read(ln_in, bv); write(ln_out, bv); writeline(file_out, ln_out); end loop; wait; end process; end text_file_read_a; text1.dat 1111 1010 text2.dat 1111 1010

  25. Write Text File (Example 1) library ieee; use ieee.std_logic_1164.all; use std.textio.all; entity text_file_write is end text_file_write; architecture text_file_write_a of text_file_write is begin process variable ln: line; variable bv: bit_vector(3 downto 0); file out_file: text is out "text1.dat"; begin bv := "1111"; write(ln, bv); writeline(out_file, ln); bv := "1010"; write(ln, bv); writeline(out_file, ln); wait; end process; end text_file_write_a; text1.dat 1111 1010

  26. Write Text File (Example 2) entity Write_File is end entity Write_File; architecture arch_Write_File of Write_File is signal A, B, C: Bit_vector(3 downto 0); begin A <= "1100"; B<="0110"; C<="0101"; Monitor: process use STD.TEXTIO.all; file F: TEXT is out "c:\test.txt"; --VHDL'87 variable L: LINE; begin WRITE (L, NOW, Left, 10); WRITE (L, A, Right, 5); WRITE (L, B, Right, 5); WRITE (L, C, Right, 5); WRITELINE (F, L); wait for 0 ns; WRITE (L, NOW, Left, 10); WRITE (L, A, Right, 5); WRITE (L, B, Right, 5); WRITE (L, C, Right, 5); WRITELINE (F, L); wait for 1 ns; WRITE (L, NOW, Left, 10); WRITE (L, A, Right, 5); WRITE (L, B, Right, 5); WRITE (L, C, Right, 5); WRITELINE (F, L); wait; end process; end architecture arch_Write_File; 10 5 5 5 0 ns 0000 0000 0000 0 ns 1100 0110 0101 1 ns 1100 0110 0101

  27. Agenda • Generate • Assert • Function Overloading • FILE IO • Text File • Binary File

  28. Read/Write Binary File • Step 1 Define File Format (Store data type) DataType • Step 2 Define user data object, DataObj • Step 3 Define File object, FileObj file FileObject: DataType is in "FileName "; file FileObject: DataType is out "FileName"; • Step 4 Define data length variable, Length • Step 5 Read/Write Data read(FileObj, DataType, Length); write(FileObj, DataObject);

  29. Write Binary File architecture file_write_a of file_write is type bit_vec is file of bit_vector; file out_file: bit_vec is out "F1.dat"; begin process variable v: bit_vector(3 downto 0); begin v := "1101"; write(out_file, v); wait for 100 ms; v := "0001"; write(out_file, v); wait for 100 ms; v := "1111"; write(out_file, v); wait for 100 ms; wait; end process; end file_write_a; library ieee; use ieee.std_logic_1164.all; use std.textio.all; entity file_write is end file_write;

  30. Read/Write Binary File architecture file_read_a of file_read is type bit_vec is file of bit_vector; file in_file: bit_vec is in "F1.dat"; file out_file: bit_vec is out "F2.dat"; begin process variable v: bit_vector(3 downto 0); variable len: natural:= 1; begin loop exit when endfile(in_file); read(in_file, v, len); write(out_file, v); wait for 100 ms; end loop; wait; end process; end file_read_a; library ieee; use ieee.std_logic_1164.all; use std.textio.all; entity file_read is end file_read;

  31. Definitions For Text File (1) package TEXTIO is -- Type definitions for text I/O: type LINE is access STRING; -- A LINE is a pointer to a STRING value. type TEXT is file of STRING; -- A file of variable-length ASCII records. type SIDE is (RIGHT, LEFT); -- For justifying output data within fields. subtype WIDTH is NATURAL; -- For specifying widths of output fields. -- Standard text files: file INPUT: TEXT open READ_MODE is "STD_INPUT"; file OUTPUT: TEXT open WRITE_MODE is "STD_OUTPUT"; -- Input routines for standard types: procedure READLINE (file F: TEXT; L: out LINE); procedure READ (L: inout LINE; VALUE: out BIT; GOOD: out BOOLEAN); procedure READ (L: inout LINE; VALUE: out BIT); procedure READ (L: inout LINE; VALUE: out BIT_VECTOR; GOOD: out BOOLEAN); procedure READ (L: inout LINE; VALUE: out BIT_VECTOR); procedure READ (L: inout LINE; VALUE: out BOOLEAN; GOOD: out BOOLEAN); procedure READ (L: inout LINE; VALUE: out BOOLEAN); procedure READ (L: inout LINE; VALUE: out CHARACTER; GOOD: out BOOLEAN);

  32. Definitions For Text File (2) procedure READ (L: inout LINE; VALUE: out CHARACTER); procedure READ (L: inout LINE; VALUE: out INTEGER; GOOD: out BOOLEAN); procedure READ (L: inout LINE; VALUE: out INTEGER); procedure READ (L: inout LINE; VALUE: out REAL; GOOD: out BOOLEAN); procedure READ (L: inout LINE; VALUE: out REAL); procedure READ (L: inout LINE; VALUE: out STRING; GOOD: out BOOLEAN); procedure READ (L: inout LINE; VALUE: out STRING); procedure READ (L: inout LINE; VALUE: out TIME; GOOD: out BOOLEAN); procedure READ (L: inout LINE; VALUE: out TIME); -- Output routines for standard types: procedure WRITELINE (file F: TEXT; L: inout LINE); procedure WRITE (L: inout LINE; VALUE: in BIT; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0); procedure WRITE (L: inout LINE; VALUE: in BIT_VECTOR; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0); procedure WRITE (L: inout LINE; VALUE: in BOOLEAN; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0); procedure WRITE (L: inout LINE; VALUE: in CHARACTER; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0);

  33. Definitions For Text File (3) procedure WRITE (L: inout LINE; VALUE: in INTEGER; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0); procedure WRITE (L: inout LINE; VALUE: in REAL; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0; DIGITS: in NATURAL:= 0); procedure WRITE (L: inout LINE; VALUE: in STRING; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0); procedure WRITE (L: inout LINE; VALUE: in TIME; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0; UNIT: in TIME:= ns); -- File position predicate: --function ENDFILE (file F: TEXT) return BOOLEAN; end TEXTIO;

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