SOC Design: From System to Transistor

1. SOC Design: From System to Transistor Zoran Stamenković

2. Outline • Modeling Systems • Simulation and Verification • Analog Integrated Circuits • Digital Integrated Circuits • Embedded Memories • Logic Synthesis • Design for Testability • Layout Generation • Design for Manufacturability • SOC Example

3. Modeling Systems • Domains and Levels • ESL Design • Basics of HDL • Gate Modeling • Delay Modeling • Power Modeling • Effects of Parasitics • Logic Optimization

4. Domains and Levels • Open Systems Interconnection (OSI) model of network communication • Local area network (LAN) technologies are defined by standards that describe unique functions at both the Physical and the Data Link layers

5. Domains and Levels • 802.11 Wireless LAN modem • Modulates outgoing digital signals from a computer or other digital device to an analogue (radio) signal • Demodulates the incoming analogue (radio) signal and converts it to a digital signal for the digital device

6. MIMO and MIMAX WLAN Modems Domains and Levels Signal processing performed in the digital baseband Signal processing performed in the analogue RF domain Number of the digital basebands reduced to a single one

7. Structural Behavioral Analysis Synthesis Refinement Generation Abstraction Extraction Physical Domains and Levels

8. Structural Behavioral Algorithm(behavioral) Register-TransferLanguage Boolean Equations Differential Equations Physical Behavioral Domain

9. Structural Behavioral Processor-MemorySystem Registers Gates Transistors Physical Structural Domain

10. Behavioral Structural Polygons Sticks Standard Cells Floor Plan Physical Physical Domain

11. Electronic System Level Design • The point of a system level model is to capture the intent of the design • Design does exactly what it is defined to do, and the model is the definition of what the design does • It allows software developers to test their code on a working model • The value of system level modeling is in helping us to understand the implications of our intent • To explore responses to the stimulus in an useful way • ESL Languages • UML, SystemC, SystemVerilog • ESL Verification • “No amount of experimentation can ever prove me right; a single experiment can prove me wrong” – Albert Einstein • The system level testbench languages and methodologies that exist today are woefully inadequate • If one tries to capture enough information in ESL to verify RTL, then one might as well write RTL

12. Complete Hardware Design Source pre-verified RTL, EDA scripts, test suite ANSI C/C++ Code int main() { int i; short c[100]; for (i=0;i<N/2;i++) { Processor Extensions Use standard ASIC/COT design techniques andlibraries for any IC fabrication process • Processor • Configuration • Select from menu • Add instruction description (TIE) • Automatic instruction discovery (XPRES) XtensaProcessorGenerator • CustomizedSoftware Tools • C/C++ compiler Debuggers Simulators • RTOSes XPRESCompiler Electronic System Level Design • The environment that provides models of memories, connectors, and queues that can be interconnected with configured processors into an overall system model • Processor and device interfaces are at the transaction level • Transaction-level modeling requests for SOC architecture assembly and simulation tools • If RTL IP blocks present, HW/SW co-verification tools needed

13. Auto-generated XTMP model based on memory maps • Specify chip-level memory maps for shared/private memories • Place interrupt and reset vectors • Assign code/data to distributed memories Electronic System Level Design

14. Hardware Description Languages • Motivation for HDL • Increased hardware complexity • Design space exploration • Inexpensive alternative to prototyping • General features • Support for describing circuit connectivity • High-level programming language support for describing behavior • Support for timing information (constraints, etc.) • Support for concurrency • VHDL • IEEE Standard 1076-1987 • IEEE Standard 1076-1993 • Extension VHDL-AMS-1999 • Verilog • IEEE Standard 1364-1995 • IEEE Standard 1364-2000

15. port mode (direction) entity reg3 isport ( d0, d1, d2, en, clk : in bit; q0, q1, q2 : out bit );end; port type (VHDL only) VHDL reserved words name port names punctuation module reg3( d0, d1, d2, en, clk, q0, q1, q2 ); input d0, d1, d2, en, clk; output q0, q1, q2; endmodule Verilog Modeling Interfaces • Entity (VHDL) or Module(Verilog) declaration • Describes the input/output ports of a module

16. Modeling Behavior • Architecture Body (VHDL) • Describes an implementation of an entity • May be several per entity • Module (Verilog) • Is unique • Behavioral Architecture • Describes the algorithm performed by the module • Contains • Procedural Statements, each containing • Sequential Statements, including • Assignment Statements and • Wait Statements

17. Behavior Example entity reg3 isport ( d0, d1, d2, en, clk : in bit; q0, q1, q2 : out bit );end; architecture behav of reg3 isbegin process ( d0, d1, d2, en, clk )beginif en = '1' and clk = '1' then q0 <= d0 after 5 ns; q1 <= d1 after 5 ns; q2 <= d2 after 5 ns; end if;end process; end; `timescale 1ns/10ps module reg3 ( d0, d1, d2, en, clk, q0, q1, q2 ); input d0, d1, d2, en, clk; output q0, q1, q2; reg q0, q1, q2; always @ ( d0 or d1 or d2 or en or clk ) if ( en & clk ) begin q0 <= #5 d0; q1 <= #5 d1; q2 <= #5 d2; end endmodule VHDL Verilog

18. Modeling Structure • Structural Architecture • Implements the module as a composition of components • Contains • Signal Declarations (entity ports are also signals) • Declare internal connections • Component Instances • Instantiate previously declared entity/architecture pairs • Port Maps in component instances • Connect signals to component ports • Wait Statements • Suspend a process or procedure

19. bit0 d _latch d0 q0 d q clk bit1 d _latch d1 q1 d q clk bit2 d _latch d2 q2 d q clk gate and2 en int _clk a y clk b Structure Example

20. entity d_latch isport ( d, clk : in bit; q : out bit );end; architecture basic of d_latch isbegin process ( d, clk )beginif clk = ‘1’ then q <= d after 5 ns;end if;end process; end; `timescale 1ns/10ps module d_latch ( d, clk, q ); input d, clk; output q; reg q; always @ ( d or clk ) if ( clk ) begin q <= #5 d; end endmodule Verilog VHDL entity and2 isport ( a, b : in bit; y : out bit );end; architecture basic of and2 isbegin process ( a, b ) begin y <= a and b after 5 ns;end process; end; `timescale 1ns/10ps module and2 ( a, b, y ); input a, b; output y; reg y; always @ ( a or b ) begin y <= #5 ( a & b ); end endmodule Verilog VHDL Structure Example

21. entity reg3 isport ( d0, d1, d2, en, clk : in bit; q0, q1, q2 : out bit );end; architecture struct of reg3 is component d_latchport ( d, clk : in bit; q : out bit );end component; component and2port ( a, b : in bit; y : out bit );end component; signal int_clk : bit; begin bit0 : d_latch port map ( d0, int_clk, q0 ); bit1 : d_latch port map ( d1, int_clk, q1 ); bit2 : d_latch port map ( d2, int_clk, q2 ); gate : and2 port map ( en, clk, int_clk ); end; module reg3 ( d0, d1, d2, en, clk, q0, q1, q2 ); input d0, d1, d2, en, clk; output q0, q1, q2; wire int_clk; d_latch bit0 ( d0, int_clk, q0 ); d_latch bit1 ( d1, int_clk, q1 ); d_latch bit2 ( d2, int_clk, q2 ); and2 gate ( en, clk, int_clk ); endmodule Verilog VHDL Structure Example

22. Mixing Behavior and Structure • An architecture can contain both behavioral and structural parts • Process Statements and Component Instances • Collectively called Concurrent Statements • Processes can read and assign to signals • Example: Register-transfer-language model • Data-path described structurally • Control section described behaviorally

23. Mixed Example

24. Mixed Example entity multiplier isport ( clk, reset : in bit; multiplicand, multiplier : in integer; product : out integer );end; architecture mixed of multiplier is signal partial_product, full_product : integer;signal arith_control, result_en, mult_bit, mult_load : bit; begin arith_unit : entity work.shift_adder(behavior)port map ( addend => multiplicand, augend => full_product, sum => partial_product, add_control => arith_control ); result : entity work.reg(behavior)port map ( d => partial_product, q => full_product, en => result_en, reset => reset ); ...

25. Mixed Example … multiplier_sr : entity work.shift_reg(behavior)port map ( d => multiplier, q => mult_bit, load => mult_load, clk => clk ); product <= full_product; control_section : process is -- variable declarations for control_section -- …begin -- sequential statements to assign values to control signals -- …wait on clk, reset;end process control_section; end;

26. Logic Functions • Function • f = a’b + ab’: a is a variable, a and a’ are literals, ab’ is a term • Irredundant Function • No literal can be removed without changing its value • Implementing logic functions is non-trivial • No logic gates in the library for all logic expressions • A logic expression may map into gates that consume a lot of area, time, or power • A set of functions f1, f2, ... is complete if every Boolean function can be generated by a combination of the functions from the set • NAND is a complete set • NOR is a complete set • AND and OR are not complete • Transmission gates are not complete • Incomplete set of logic gates • No way to design arbitrary logic

27. + a a out c Inverter

28. Inverter

29. Switches • Complementary switch produces full-supply voltages for both logic 0 and logic 1 • n-type transistor conducts logic 0 • p-type transistor conducts logic 1

30. VDD + out tub ties out b a b a GND NAND Gate

31. VDD b tub ties a b out out GND a NOR Gate

32. invert or and AOI/OAI Gates • AOI = and/or/invert • OAI = or/and/invert • Implement larger functions • Pull-up and pull-down networks are compact • Smaller area, higher speed than NAND/NOR network equivalents • AOI312 • And 3 inputs • And 1 input (dummy) • And 2 inputs • Or together these terms • Invert out = [ab+c]’

33. VDD logic 1 VH unknown VL logic 0 VSS Logic Levels • Solid logic 0/1 defined by VSS/VDD • Inner bounds of logic values VL/VH are not directly determined by circuit properties, as in some other logic families • Levels at output of one gate must be sufficient to drive next gate

34. Inverter Transfer Curve • Choose threshold voltages at points where slope of transfer curve is -1 • Inverter has • High gain between VIL and VIH points • Low gain at outer regions of transfer curve • Note that logic 0 and 1 regions are not equally sized • In this case, high pull-up resistance leads to smaller logic 1 range • Noise margins are VDD-VIH and VIL-VSS • Noise must exceed noise margin to make second gate produce wrong output

35. Inverter Delay • Only one transistor is on at the time • Rise time (pull-up on) • Fall time (pull-up off) • Resistor model of transistor • Ignores saturation region • Mischaracterizes linear region • Gives acceptable results

36. RC Model for Delay • Delay • Time required for gate’s output to reach 50% of final value • Transition time • Time required for gate’s output to reach 10% (logic 0) or 90% (logic 1) of final value • Gate delay based on RC time constant • Vout(t) = VDD exp{-t/[(Rn+RL)CL]} • td = 0.69 RnCL • tf = 2.3 RnCL • 0.5 mm process • Rn = 3.9 kW • CL = 0.68 fF • td = 0.69 x 3.9 x .68E-15 = 1.8 ps • tf = 2.3 x 3.9 x .68E-15 = 6.1 ps • For pull-up time, use pull-up resistance • Current source model (in power/delay studies) • tf = CL (VDD-VSS)/[0.5 k’ (W/L) (VDD-VSS -Vt)2] • Fitted model • Fit curve to measured circuit characteristics

37. Step Input (VGS = VDD) Approximation

38. 0 Source above VSS 0 Early arriving signal Body Effect • Source voltage of gates in middle of network may not equal substrate voltage • Difference between source and substrate voltages causes body effect • To minimize body effect • Put early arriving signals at transistors closest to power supply

39. Power Consumption • Clock frequency • f = 1/t • Energy • E = CL(VDD - VSS)2 • Power • E x f = f CL(VDD - VSS)2 • Almost all power consumption comes from switching behavior • A single cycle requires one charge and one discharge of capacitor • Static power dissipation • Comes from leakage currents • Surprising result • Resistance of the pull-up/pull-down transistor drops out of energy calculation • Power consumption is independent of the sizes of the pull-up and pull-down transistors • Static CMOS power-delay product is independent of frequency • Voltage scaling depends on this fact

40. Effects of Parasitics • Capacitance on power supply is not bad • Can be good in absence of inductance • Resistance slows down static gates • May cause pseudo-nMOS circuits to fail • Increasing capacitance/resistance • Reduces input slope • Resistance near source is more damaging • It must charge more capacitance

41. Optimal Sizing • Sometimes, large loads must be driven • Off-chip or by long wires on-chip • Sizing up the driver transistors only pushes back the problem • Driver now presents larger capacitance to earlier stage • Use a chain of inverters • Each stage has transistors larger than previous stage • a is the driver size ratio, Cbig/Cd= an, ln(Cbig/Cd) = n lna • Minimize total delay through the driver chain • ttot = ln(Cbig/Cd)(a/lna)td • Optimal driver size ratio is aopt = e • Optimal number of stages is nopt = ln(Cbig/Cd)

42. Driving Large Fan-Out • Fan-out adds capacitance • Increase sizes of driver transistors • Must take into account rules for driving large loads • Add intermediate buffers • This may require/allow restructuring of the logic

43. Path Delay • Network delay is measured over paths through network • Can trace a causality chain from inputs to worst-case output • Critical path creates longest delay • Can trace transitions which cause delays that are elements of the critical path delay • To reduce circuit delay, speed up the critical path • Reducing delay off the path doesn’t help • There may be more than one path of the same delay • Must speed up all equivalent paths to speed up circuit

44. False Paths • Logic gates are not simple nodes • Some input changes don’t cause output changes • A false path is a path which cannot be exercised due to Boolean gate conditions • False paths cause pessimistic delay estimates

45. Logic Transformations • Rewrite by using sub-expressions • Logic rewrites may affect gate placement • Flattening logic • Increases gate fan-in • Logic synthesis programs • Transform Boolean expressions into logic gate networks in a particular library Shallow Logic Deep Logic

46. Logic Optimization • Optimization goals • Minimize area, meet delay constraint • Technology-independent optimization • Works on Boolean expression equivalent • Estimates size based on number of literals • Uses factorization, resubstitution, minimization, etc. • Uses simple delay models • Technology-dependent optimization • Maps Boolean expressions into a particular cell library • May perform some optimizations on addition to simple mapping • Allows more accurate delay models

47. Simulation and Verification • Simulation • Verification • Annotation

48. Simulation • Simulation • Tests the functionality of a design’s elaborated model • Needs a test bench and a simulation tool • Advances in discrete time steps • Test Bench • Includes an instance of the design under test • Applies sequences of test values to inputs • Monitors signal values on outputs using simulator • Simulation Tools • NCSIM (Cadence) • VSIM (Mentor Graphics) • VCS (Synopsys)

49. Event-Driven Simulation • Event-driven simulation is designed for digital circuit characteristics • Small number of signal values • Relatively sparse activity over time • Event-driven simulators try to update only those signals which change in order to reduce CPU time requirements • An event is a change in a signal value • A time-wheel is a queue of events • Simulator traces structure of circuit to determine causality of events • Event at input of one gate may cause new event at gate’s output

50. A C D B Switch Simulation • Special type of event-driven simulation optimized for MOS transistors • Treats the transistor as a switch • Takes capacitance into account to model charge sharing • Can also be enhanced to model the transistor as a resistive switch