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Understanding Virtual Memory and Memory Hierarchy Implementation

This chapter explores virtual memory, memory hierarchy, and implementation details such as paging, cache, and translation. Learn about the role of hard drives, protection mechanisms, and multi-processing with virtual memory. Discover how page faults, TLB, and page tables work in maintaining efficient memory operations.

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Understanding Virtual Memory and Memory Hierarchy Implementation

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  1. Virtual Memory Chapter 7.4

  2. DRAM as cache • What about programs larger than DRAM? • When we run multiple programs, all must fit in DRAM! • Add another larger, slower level to the memory hierarchy - use part of the hard drive.

  3. Virtual Memory • Memory Size - • Protection -

  4. Multi-Processing - no VM Prog A • Program A begins • Program B begins Prog B What happens if A wants more memory?

  5. Multi-Processing - no VM • Program A begins • Program B begins • Program A ends • Program C ready Can C run? Prog C Prog B

  6. Virtual Memory • Use hard drive for memory that does not fit in DRAM • Allocate memory in pages • Provide protection by page

  7. Address Space • Virtual Address Space • Physical Address Space

  8. Multi-Processing - VM Virtual Address Physical Address 0 • Program A begins • Program B begins Prog A 16K 0 Prog B 24K Hard Drive

  9. Hard Drive Multi-Processing - VM Virtual Address Physical Address 0 Prog A • Program A begins • Program B begins 20K What happens if A wants more memory?Allocate another virtual page. 0 Prog B 24K

  10. Hard Drive Multi-Processing - VM Virtual Address 0 Physical Address • Program A begins • Program B begins • Program A ends • Program C begins • Not all placed in DRAM • DRAM use need not be contiguous Prog C 28K 0 Prog B 24K

  11. Virtual Memory is like caching… • _______ is the cache for the __________ • It contains only a subset of the total space • Given an address, determine whether it is currently in the “cache” • On a miss, obtain data and place in “cache”

  12. Virtual Memory is not like caching… • The miss penalty is orders of magnitude larger than for the cache • You must know where it resides in DRAM before you can look it up in L1 cache • This leads to a much different implementation

  13. The Search • Cache – search each block in set for the proper tag • Virtual Memory – store a table that is a mapping from virtual address to physical location (in DRAM).

  14. Virtual Memory Implementation • Programs use addresses • VM Block is called a __________ • A VM DRAM “cache miss” is called a ______________. • To access data, the address must translate it to a _______________. • This translation is called _______________ or ________________.

  15. Virtual Memory Implementation • Translation process: • Why is Physical address smaller than Virtual? Virtual page number Page offset Translation Physical page number Page offset

  16. Virtual Memory ImplementationPage faults incredibly costly • DRAM is a cache - • Direct-mapped? • Set-associative? • Fully associative? • Low associativity • miss rate, search time • High associativity • miss rate, search time

  17. Virtual Memory ImplementationPage faults incredibly costly • Associativity: ________________ • Block size: ________________ • Sophisticated software to implement replacement policy • updates are hidden under ______________ • Write policy:

  18. Translation • Does the same virtual address always translate to the same physical address? • How often does a translation occur?

  19. Translation • Maintaining per process page tables • Process page table maintained by ____ - ___________________________ • Making translations fast • Use a Translation Lookaside Buffer (_____) to cache recent translations • Fully associative but ____________________

  20. Step 1: TLB • Search all locations of TLB in parallel Virtual page number Page offset VPN PPN Physical page number Page offset

  21. Step 1: TLB • Search all locations of TLB in parallel • Hit - • Miss -

  22. Step 2: TLB Miss • Access the process’ page table to retrieve translation • If valid (DRAM hit) • fill in TLB with this entry • restart TLB access and translation • If invalid, we have a page fault

  23. Step 3: Page Fault • Operating System invoked to swap a page in DRAM with the page requested on hard drive. • Operating system looks up page’s location on hard drive. • Operating system maintains replacement algorithm • OS updates the process’ page tables

  24. Putting it all together Yes No No Yes Write? No Yes Write access bit on? No Yes

  25. TLB • How can a 16-64 entry TLB be enough for 512MB of RAM? (L2 cache-512KB) Virtual page number Page offset Translation

  26. Protection • Preventing A from reading B’s data • Allowing A to share data with B • Prevent overwriting instructions • Prevent stack smashing (popular attack)

  27. Virtual Memory Summary • VM increases total available memory • VM provides multi-process protection • TLB is necessary for fast translations • OS manages virtual memory

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