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Device: WP2 Interface & materials

Device: WP2 Interface & materials. Amit K. Tiwari , Nick Wright and Anthony O’Neill School of Electrical and Electronic Engineering Newcastle University amit.tiwari@ncl.ac.uk , nick.wright@ncl.ac.uk and anthony.oneill@ncl.ac.uk. Our research work area.

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Device: WP2 Interface & materials

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  1. Device: WP2 Interface & materials Amit K. Tiwari, Nick Wright and Anthony O’Neill School of Electrical and Electronic Engineering Newcastle University amit.tiwari@ncl.ac.uk, nick.wright@ncl.ac.ukand anthony.oneill@ncl.ac.uk

  2. Our research work area • Designing, parameter optimisation and performance evaluations of power semiconductor devices1 • (static, transient, electro-thermal, breakdown analyses) Hot spot Lateral JFET Self-heating analysis Breakdown Vertical JFET 1. High voltage 4H-SiC current limiting device for serial protection applications, submitted to ECSCRM2014. 2. Design optimization and performance evaluation of a 10 kV super-junction power SiC-JFET, submitted to ECSCRM2014. 3. Self-heating effects in lateral JFETs, in preparation for IEEE TED. Breakdown-analysis Transient analysis Contd...

  3. 2. Device fabrication and characterisation SEM image of cross-section of a lateral FET 1. Manuscript in preparation Vov=Vgs-VT Contd...

  4. 3. Modelling of wide bandgap materials (SiC and diamond) and surface/interfaces analysis Electronic affinity calculation for H- and O-terminated diamond surfaces [001] Oriented metal terminated diamond surface (a) Surface topography and (b) contact potential difference (Kelvin probe measurement) map for a nano-crystalline diamond surface Electronic and structural properties of diamond (100) surfaces terminated by selected transition metals, PRB 86 155301. Calculated electron affinity and stability of halogen-terminated diamond, PRB 84245305 3. Tuning optoelectronic properties of 4H-SiC QDs using -H, -OH and -F surface functionalisation, submitted to ECSCRM2014. 4H-SiC (Si-face) 4H-SiC (C-face)

  5. Ln<Lp Ln>Lp Ln=Lp Project Plans & Objectives • Designing and performance evaluation of novel high temperature and high voltage SiC devices for rugged electronic applications (our current main focus is on the super-junction structures) • Development of fabrication process steps and high temperature device packaging analysis for thermal management • Extreme environments testing Super-junction VJFET structure 1. Design optimization and performance evaluation of high voltage (>1 kV) super–junction SiC–JFETs, in preparation for IEEE TED. Charge-imbalence analysis

  6. Potential Outcomes & Exploitation Plans Outcomes: Commercially unavailable novel high temperature and high voltage SiC-devices Advancement of underpinning material growth and device fabrication technology Exploitation: Technology dissemination to the wider power-electronics community working in different areas (aerospace, automobile and power distribution sectors) through the knowledge transfer networks and potential collaborations. Publications in refereed academic journals and conferences, and feature articles in trade journals

  7. Input from the PE Community Any experience/feedback regarding the super-junction and electro-thermal simulations of thick device (several 100s microns) structures will be much appreciated.

  8. Thanks

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