US CMS SLHC Muon Trigger R&D

1. US CMS SLHC Muon Trigger R&D Darin Acosta University of Florida (on behalf of CSC trigger groups)

2. Present CSC Muon Trigger, Schematic D M B T M B D M B T M B D M B T M B D M B T M B C C B T M B D M B T M B D M B T M B D M B T M B D M B D M B T M B M P C C O N T R O L L E R 1 of 5 1 of 5 Cathode Front-end Board CFEB CFEB CFEB CFEB CFEB 1 of 2 1 of 24 ALCT LVDB Anode Front-end Board CSC *upgrade paths *Muon Portcard (1/crate) (Rice) Trigger Motherboard (9/crate) *Clock Control Board DAQ Motherboard (9/crate) Trigger Timing & Control Optical links Peripheral Crate on iron disk (1 of 60) *Sector Processor (12) (U. Florida) *Muon Sorter (1) (Rice) *CSC Track-Finder Crate (1) Anode LCT Board In underground counting room On detector Trigger Primitives 3-D Track-Finding and Measurement LCT=Local Charged Track USCMS Meeting - SLHC Muon Trigger R&D

3. Present CSC Muon Trigger, Photos Boards from UF and Rice Univ. Data source from the peripheral crates and the anode/cathode front-ends(ALCT, TMB, MPC) Sector processors, clock & control, muon sorter USCMS Meeting - SLHC Muon Trigger R&D

4. LHC Upgrade of CSC Track-Finder Mezzanine Cards • FY08 upgrade conducted to replace the mezzanine cards on the Sector Processors with a larger Xilinx Virtex-5 FPGA for LHC operations • Accommodates 3X more logicthan previous Virtex-2chip that was 90% full • Scope of CSCTF had increased since original design for commissioning and startup: beam halo trigger, single LCT trigger • New logic can accommodate additional extrapolations for higher efficiency, better Pt measurement for showering muons, better ghost cancellation, and refined halo trigger • Production of 20 cards complete Feb.’09, testing succeeded, and installation of 12 complete in Mar.’09. • Successfully used in last two midweek global runs USCMS Meeting - SLHC Muon Trigger R&D

5. Motivation for Upgrading CSC Trigger for SLHC • Occupancies in CSC system will increase at SLHC • For end of phase 2 (L1035), and 50ns bunch spacing, expect 20X more prompt pile-up (400 collisions) and much larger neutron background • Combination with inner Tracker information for SLHC phase 2 requires delivering all appropriate information to define roads in Tracker layers, at necessary precision • Upgraded pixel detector in phase 1 also could possibly allow for a proof-of-principle tracking trigger • Aim for a single CSC muon trigger upgrade to accommodate both Phase 1 and Phase 2 requirements USCMS Meeting - SLHC Muon Trigger R&D

6. USCMS Meeting - SLHC Muon Trigger R&D

7. CSC SLHC Simulation Studies V.Khotilovich, A.Safonov (TAMU) • Set up full simulation in CMSW to quantitatively describe detector and trigger for SLHC pile-up scenarios • Special modifications needed • Challenges of memory consumption • Studies of present CSC trigger performance with SLHC pile-up (prompt) • Including re-scoping ME4/2, and ME1/1a in trigger • Trigger primitive performance (efficiency, timing) • Track-Finder performance • Occupancy • Need effort to address neutron background (long-time pile-up) • Old methods/parameterizations need adapting • Could be dominant source of occupancy! USCMS Meeting - SLHC Muon Trigger R&D

8. CSC Trigger Efficiencies • Efficiency with ME4/2 rescoped • Blue = best tracks • Green = next best • Red = low quality, no PT info • With pile-up: • Improvements to trigger primitive logic will be needed (expected) USCMS Meeting - SLHC Muon Trigger R&D

9. Trigger Primitive Occupancy at MPC • Using CMS Note 2002/007 (UCLA) and studies from TAMU, calculate possible LCT occupancy for SLHC luminosities of phase 2 (L=1035) and 50ns spacing • i.e. 400 p/u events • Preliminary occupancy estimate per MPC per BX, with 2 fluctuations and a guestimate on neutron the background: • Occupancy= 0.25 +2*0.6 (prompt p/u + 2 fluctuation) + 2.5*1.5 (scale by 250% for neutrons) = 5 LCT • Add two signal muons in a given 60° sector  7 LCT • Need to add safety factor on top of this, until backgrounds measured at LHC USCMS Meeting - SLHC Muon Trigger R&D

10. Phase 1 CSC Trigger Upgrade Constraints • Accommodate higher SLHC occupancy to CSCTF • Increase bandwidth from MPC beyond 3 LCTs/BX for additional LCTs/sector (upgraded optical links) • Additional sorter outputs from MPC • Increased logic for track building • Keep limit of 2 LCTs/BX from each CSC • Natural limit of CSCs because of ghosting • Avoid peripheral crate backplane redesign • Avoid system-wide hardware upgrade of ALCT, TMB (540 CSCs) • WILL require changes in firmware for LCT timing and logic, plus: • Accommodate Digital CFEB upgrade for recovering ME1/1a • TMB hardware upgrade (new optical link connections), and firmware • Subject to constraints of existing system (backplane to MPC) • Flexibility to send muon outputs to a prototype Phase 2 tracking trigger • Stay within fixed 3.6s latency • Evolutionary upgrade: phase in new components in parallel with existing system, and/or deploy same functionality on new cards • Active splitters in system USCMS Meeting - SLHC Muon Trigger R&D

11. Muon Port Card Upgrade Directions • The Muon Port Card is a “choke point” in the CSC trigger path (by design, to reduce optical link costs) • Sorts and filters up to 18 LCTs from 9 chambers to a maximum of only 3 • Assuming 2 LCTs are signal, allowing 1 for background is not enough for SLHC occupancies (beyond L=1034) • Triggering on ME1/1a may add still additional LCTs • MPC needs to be redesigned to allow more throughput • Investigate additional sorting logic to send N>3 LCTs • Investigate higher bandwidth optical links • Keep 3 links of original type in addition to new links to maintain existing CSCTF crate while commissioning new one • MPC becomes the active splitter in the system • Will need to blow additional fibers from UXC to USC USCMS Meeting - SLHC Muon Trigger R&D

12. MPC Sorting Studies M.Matveev, Rice • Expanded MPC logic only requires 15% more logic for N=7 • Fits in existing FPGA and adds 2 BX latency • Preliminary testing of algorithm USCMS Meeting - SLHC Muon Trigger R&D

13. Optical Link Technology Investigation • Max number of optical links from one MPC to Sector Processor (for 32-bit LCT@40MHz, all CSCs): • 9 @ 3.2Gbps • 6 @ 4.8Gbps • 3 @ 9.6Gbps [Currently 3 @ 1.6Gbps] M.Matveev, Rice USCMS Meeting - SLHC Muon Trigger R&D

14. R&D on 10 Gbps Link in 2007: ALCT with new Mezzanine board A.Madorsky, UF Link reference oscillator EG-2101CA 161.1328M-PCHL3 10.3125 Gbps optical transceiver PICOLIGHT PL-XXL-SC-S45-21 Serializer MAX3952 Deserializer MAX3953  No longer available Front-end Clock and Time marker Reset inputs FPGA XC4VLX25-11FF668 New Inputs from front-end comparators Existing motherboard 10.3125 Gbps eye diagram (receiver’s electrical output after 100 m of fiber) USCMS Meeting - SLHC Muon Trigger R&D

15. Sector Processor Upgrade Directions • Accept higher number of LCTs/BX from each MPC for robustness against SLHC occupancy • Maximum number would be 18 LCTs (2 LCTs/CSC), i.e. no sorting • Receive higher bandwidth optical link data from MPC • Investigate a new solution for the geometry conversion LUTs • 45 LUTs  300! • Investigate logic resources required for track-finding with increased combinatorics • Naively, ~182/32  40X more resources! • Scrub logic to minimum necessary to achieve performance • Investigate higher precision on track quantities • Eta, phi, pT (?) USCMS Meeting - SLHC Muon Trigger R&D

16. Geometry Conversion • Reason • Convert LCT pattern labels into  and  coordinates for tracking • LHC implementation • External LUTs, whichwill grow in number for SLHC… • SLHC • Embed simple conversions into FPGA(s) • Work directly in global strip (~) and wire (~radius) units • Don’t perform alignment corrections until output (PT calc.) • Take advantage of linear parameterizations of conversions recently developed for CMSSW emulator • And translate cuts on  to equivalent cuts on R • Seems feasible USCMS Meeting - SLHC Muon Trigger R&D

17. Geometry Mapping for Track Building • Consider only physically allowed chamber combinations from one disk to the next in track extrapolations and in track building to reduce logic resources • Not all combinations need testing due to limited bending in magnetic field (<10°) ME1 to ME2,3,4 Total: 68 paths ME2,3,4 to ME2,3,4 Total: 33 paths - means path to chamber directly behind USCMS Meeting - SLHC Muon Trigger R&D

18. Number of extrapolations as a measure of the logic resources • Original CSCTF handled 63 extraps, new option is ~20X larger • But current FPGAs are 3X larger than original 2002 design • Would need another ~7X increase by time of SLHC Phase 1 Achieves 2.5X reduction from maximum n.b. Additional combinations for ME1/1a? For combinations from neighbor sectors? USCMS Meeting - SLHC Muon Trigger R&D

19. Further Design Considerations & Options • Additional modifications for CSCTF logic • Consider CSC segment sharing across sector boundaries? • Better efficiency across phi boundaries • Extend ghost-busting logic to all chambers when 2 LCTs/CSC • Try all wire-strip combinations in each CSC • Include alignment corrections into PT assignment logic • Improve PT assignment algorithm • Improved precision on quantities going into larger LUT, further refinement of algos in FPGA • Beyond CSCTF • Look at how to use CSCTF information to match to track stubs/tracklets from a Tracker trigger for SLHC Phase 2 • Only way to control muon rates at SLHC by improving PT resolution, adding vertex finding, and muon isolation • Feedback needs of matching to Tracker into design of CSCTF • Send muons from each sector, or from system overall? • Extrapolate muon to vertex, to tracker layers? USCMS Meeting - SLHC Muon Trigger R&D

20. Phase 1 CSC Trigger R&D Summary • Simulations: • Develop/refine trigger emulators for SLHC • Account for neutron background (long-time pile-up). New studies needed + framework development • Continue simulations with pile-up to study performance of system • Conceptual Design: • Complete a Phase 1 conceptual design to understand the scope, feasibility, and estimated cost of the system • MPC to CSCTF data transmission: • Need a prototyping round of optical transceivers + serdes operating at O(10) Gbps distributed across multiple cards • CSCTF Logic: • Develop firmware for SLHC track-finding logic to assess feasibility and resource requirement • Prototype logic on next-generation FPGA technology (e.g. Virtex-6) • CSCTF Backplane • Prototype a higher bandwidth backplane technology for the CSCTF crate. Needed to handle increased SLHC occupancy and higher precision output (current BW to sorter is saturated) • Alternative technologies • Micro-TCA standard for cards and communication • Associative memory for track-finding logic (AM++ chip from Pisa) USCMS Meeting - SLHC Muon Trigger R&D

21. Phase 1 Upgrade Projects & Group Plans • New TMB for ME1/1 chambers (EMU Project) • Texas A&M, UCLA • New MPC (links, additional sorting) • Rice U. • Active splitters (possibly part of new MPC) • Rice U. • New Sector Processors (links, tracking logic, technology R&D) • Univ. Florida • New Muon Sorter (for a new GMT) • Rice U. • Track-Finder Backplane (finer info, more candidates) • Univ. Florida • Software support • Texas A&M, Univ. Florida – currently doing it, but support needed! USCMS Meeting - SLHC Muon Trigger R&D

22. Phase 2 CSC Trigger R&D • Constraints: • Stay within an increased latency of 6.2 us • In order to accommodate new tracker-muon matching logic, implies keeping ~same latency for CSC trigger up to Track-Finder • Adapt to new TTC signals • Allow for combined CSC-Tracker trigger to improve trigger performance (Pt resolution, vertexing, isolation) • New CCB (new TTC, control signals) • Rice • Further upgraded CSC system? (EMU) • TMBs system-wide? • Track-Finder outputs to Tracker-matching Trigger • Florida USCMS Meeting - SLHC Muon Trigger R&D

23. Backup