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SLINK

SLINK. Current Progress. Transition Card (ECAL). Slink Transmitter. Generic PCI Card. Slink Receiver. Hardware Setup. Control via VXI-MXI-2. FED Controller. VME Backplane. FED. LVDS Cable. Slink Controller. Configure FED to send test patterns: Simple counter

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SLINK

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  1. SLINK Current Progress James Leaver

  2. Transition Card (ECAL) Slink Transmitter Generic PCI Card Slink Receiver Hardware Setup Control via VXI-MXI-2 FED Controller VME Backplane FED LVDS Cable Slink Controller James Leaver

  3. Configure FED to send test patterns: Simple counter Alternate lines of all As and all 5s Drive FED with software triggers: Throttle triggers using software ‘waits’ and by setting QDR buffer occupancy thresholds Simply receives all data sent from FED Compares received data with current expected test pattern Slink Verification FED PC SLINK PC James Leaver

  4. Green: Slink CLK Yellow: Write Enable Blue: Bit 0 of Data Stream Pink: Bit 1 of Data Stream Example Data Transmission Test Pattern: Alternate lines of As and 5s, Scope Length: 10 Measured from Transition Card James Leaver

  5. Green: Slink CLK Yellow: Write Enable Blue: Bit 0 of Data Stream Pink: Bit 1 of Data Stream A Bad Clock? Test Pattern: Alternate lines of As and 5s, Scope Length: 10 Measured from Transition Card, Persistent Display James Leaver

  6. Green: Slink CLK Yellow: Write Enable Blue: Bit 0 of Data Stream Pink: Bit 1 of Data Stream Clock Signal at the FED Measured on the FED; Slink Connected James Leaver

  7. Clock Signal at the FED Measured on the FED; Transition Card Disconnected Green: Slink CLK Yellow: Write Enable Blue: Bit 0 of Data Stream Pink: Bit 1 of Data Stream James Leaver

  8. Spice Model of Clock Path James Leaver

  9. Spice Model Results Blue: CLK at FED VME connector Red: CLK at output connector on Transition Card Yellow: CLK at input to Transmitter FPGA James Leaver

  10. The Only Way to Remove Reflections…? James Leaver

  11. The Only Way to Remove Reflections…? CLK is good at all locations – but impractical hardware solution James Leaver

  12. Clock at Input to Transmitter FPGA The Slink clock is clean where it matters, as Spice model predicts James Leaver

  13. Slink Error Rates • Have sent 18.3 Gbytes of data from FED to Slink Receiver • Used alternate lines of all As and all 5s; highest possible switching rate • No errors observed in transmitted data •  Probability that a word will be transmitted incorrectly via Slink is: 1.22 x 10-9 @ 95% CL James Leaver

  14. Required Data Rates • To guarantee (95% CL) that no more than 1 word will be sent incorrectly per month of normal LHC operation, need to transmit words (without errors) • At current maximum data rate, would take ~16 years! • Need to find a way to increase data rate: • Could potentially output ~600 Mbytes/sec from the FED (reducing validation time to ~30 days) James Leaver

  15. FED Behaviour at High Data Rates An Extreme Example Test Pattern: Alternate lines of all As and all 5s, Scope Length: 1020 • With a fixed wait of > 60.07ms between software triggers: • QDR buffer always empty when next trigger arrives • FED operates normally • With a fixed wait of < 60.07ms between software triggers: • QDR buffer rapidly fills to current limit (1→ 10 frames) • FED operates normally for some period of time • FED randomly stops sending data James Leaver

  16. Why Does the FED Stop? x • Backpressure from the Slink? • At high trigger rates, backpressure is exerted multiple times during period in which FED is working • Overflow of QDR Buffer? • FED stops working even with a QDR buffer limit of 1 frame • Overflow of Front End Buffer? • Backend Status Register would indicate not… • But getChannelBufferOccupancy() function in ‘Fed9U’ software returns dubious values • Seems most likely cause x ? James Leaver

  17. Data Rate Challenges • Need to prevent FED lock-ups • Software triggers insufficient • Limited to a maximum of ~100 Hz • Need to use hardware triggers - generated with FED Tester? • Need to increase efficiency with which Slink PC manages received data • Currently have to run Slink software in ‘debug’ mode (raw data access) due to mismatch between output FED header/trailer words and format required for automatic event handling James Leaver

  18. Conclusion • Data can be read from the FED via Slink • No errors yet observed • Nothing to suggest that FED hardware requires modification • Firmware/Data Rate issues to be resolved… James Leaver

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