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This chapter explores the concept of Register Transfer Level (RTL) from multiple perspectives—software developers view RTL as Register Transfer Language, while microprocessor designers see it as a pseudo code for instruction set architecture. For FPGA designers, RTL represents a low-level abstraction for digital circuits. The synthesis process is crucial, translating Hardware Description Language (HDL) design into an RTL description, producing a netlist file for place-and-route tools, essential for effective design implementation.
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RTL • To software developers • RTL may mean register transfer language • To microprocessor designers • RTL may be conceived as a pseudo-code description of an instruction set architecture, describing the data flow between different elements of the processor • To FPGA designers • RTL stands for register transfer level, a relatively low level of abstraction allowing the description of a specific digital circuit
RTL Example if rising_edge (CLK) then PROD1 = A*C; PROD2 = B*D; PROD3 = A*D; PROD4 = B*C; Xr = PROD1-PROD2; Xi = PROD3 + PROD4; end if;
Synthesis • Logical Synthesis • The process of translating an HDL language design description into an RTL design description • The output of the synthesis process is a netlist file, which is used as an input to the place-and-route tools • A common format for the output netlist file is electronic design interchange format (EDIF)
Specify the Design Constraints • Determine • Design clock frequency • Input signal delays • Required output timing to signal destination • Input signal edge rates • Drive strength of input signals • Signal load within the FPGA • Operational conditions for the FPGA
